106 static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg)  in mid_pwr_get_state()  argument
108 	return readl(pwr->regs + PM_SSS(reg));  in mid_pwr_get_state()
111 static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value)  in mid_pwr_set_state()  argument
113 	writel(value, pwr->regs + PM_SSC(reg));  in mid_pwr_set_state()
116 static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value)  in mid_pwr_set_wake()  argument
118 	writel(value, pwr->regs + PM_WKC(reg));  in mid_pwr_set_wake()
121 static void mid_pwr_interrupt_disable(struct mid_pwr *pwr)  in mid_pwr_interrupt_disable()  argument
123 	writel(~PM_ICS_IE, pwr->regs + PM_ICS);  in mid_pwr_interrupt_disable()
126 static bool mid_pwr_is_busy(struct mid_pwr *pwr)  in mid_pwr_is_busy()  argument
128 	return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);  in mid_pwr_is_busy()
132 static int mid_pwr_wait(struct mid_pwr *pwr)  in mid_pwr_wait()  argument
138 		busy = mid_pwr_is_busy(pwr);  in mid_pwr_wait()
147 static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)  in mid_pwr_wait_for_cmd()  argument
149 	writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);  in mid_pwr_wait_for_cmd()
150 	return mid_pwr_wait(pwr);  in mid_pwr_wait_for_cmd()
153 static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new)  in __update_power_state()  argument
160 	power = mid_pwr_get_state(pwr, reg);  in __update_power_state()
166 	mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit));  in __update_power_state()
169 	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);  in __update_power_state()
174 	power = mid_pwr_get_state(pwr, reg);  in __update_power_state()
213 static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,  in __set_power_state()  argument
219 	state = __find_weakest_power_state(pwr->lss[id], pdev, state);  in __set_power_state()
222 	ret = __update_power_state(pwr, reg, bit, (__force int)state);  in __set_power_state()
232 static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,  in mid_pwr_set_power_state()  argument
251 	mutex_lock(&pwr->lock);  in mid_pwr_set_power_state()
252 	ret = __set_power_state(pwr, pdev, state, id, reg, bit);  in mid_pwr_set_power_state()
253 	mutex_unlock(&pwr->lock);  in mid_pwr_set_power_state()
259 	struct mid_pwr *pwr = midpwr;  in intel_mid_pci_set_power_state()  local
264 	if (pwr && pwr->available)  in intel_mid_pci_set_power_state()
265 		ret = mid_pwr_set_power_state(pwr, pdev, state);  in intel_mid_pci_set_power_state()
273 	struct mid_pwr *pwr = midpwr;  in intel_mid_pci_get_power_state()  local
277 	if (!pwr || !pwr->available)  in intel_mid_pci_get_power_state()
286 	power = mid_pwr_get_state(pwr, reg);  in intel_mid_pci_get_power_state()
292 	struct mid_pwr *pwr = midpwr;  in intel_mid_pwr_power_off()  local
300 	writel(cmd, pwr->regs + PM_CMD);  in intel_mid_pwr_power_off()
301 	mid_pwr_wait(pwr);  in intel_mid_pwr_power_off()
331 	struct mid_pwr *pwr = dev_id;  in mid_pwr_irq_handler()  local
334 	ics = readl(pwr->regs + PM_ICS);  in mid_pwr_irq_handler()
338 	writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);  in mid_pwr_irq_handler()
340 	dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));  in mid_pwr_irq_handler()
345 	int (*set_initial_state)(struct mid_pwr *pwr);
352 	struct mid_pwr *pwr;  in mid_pwr_probe()  local
367 	pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);  in mid_pwr_probe()
368 	if (!pwr)  in mid_pwr_probe()
371 	pwr->dev = dev;  in mid_pwr_probe()
372 	pwr->regs = pcim_iomap_table(pdev)[0];  in mid_pwr_probe()
373 	pwr->irq = pdev->irq;  in mid_pwr_probe()
375 	mutex_init(&pwr->lock);  in mid_pwr_probe()
378 	mid_pwr_interrupt_disable(pwr);  in mid_pwr_probe()
381 		ret = info->set_initial_state(pwr);  in mid_pwr_probe()
387 			       IRQF_NO_SUSPEND, pci_name(pdev), pwr);  in mid_pwr_probe()
391 	pwr->available = true;  in mid_pwr_probe()
392 	midpwr = pwr;  in mid_pwr_probe()
394 	pci_set_drvdata(pdev, pwr);  in mid_pwr_probe()
398 static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states)  in mid_set_initial_state()  argument
409 	mid_pwr_set_wake(pwr, 0, 0xffffffff);  in mid_set_initial_state()
410 	mid_pwr_set_wake(pwr, 1, 0xffffffff);  in mid_set_initial_state()
423 	mid_pwr_set_state(pwr, 0, states[0]);  in mid_set_initial_state()
424 	mid_pwr_set_state(pwr, 1, states[1]);  in mid_set_initial_state()
425 	mid_pwr_set_state(pwr, 2, states[2]);  in mid_set_initial_state()
426 	mid_pwr_set_state(pwr, 3, states[3]);  in mid_set_initial_state()
429 	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);  in mid_set_initial_state()
435 			pwr->lss[i][j].state = PCI_D3hot;  in mid_set_initial_state()
441 static int pnw_set_initial_state(struct mid_pwr *pwr)  in pnw_set_initial_state()  argument
450 	return mid_set_initial_state(pwr, states);  in pnw_set_initial_state()
453 static int tng_set_initial_state(struct mid_pwr *pwr)  in tng_set_initial_state()  argument
461 	return mid_set_initial_state(pwr, states);  in tng_set_initial_state()