Lines Matching +full:4 +full:kb
39 #define KB (1024) macro
51 pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4, in reg_init()
68 pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4, in sata_reg_init()
100 DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
101 DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
102 DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
103 DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
104 DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
105 DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
106 DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
108 DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
109 DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
111 DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
122 DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write)
123 DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
125 DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
127 DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
130 DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
131 DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
139 DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
140 DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
141 DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
145 DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
146 DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
165 mask = 0xFFFFFFFF >> ((4 - len) * 8); in extract_bytes()
187 if (len == 4) in bridge_read()
199 PCI_BASE_ADDRESS_0, 4, &av_bridge_base); in bridge_read()