3  * KVM PMU support for AMD
20 #include "pmu.h"
28 static struct kvm_pmc *amd_pmu_get_pmc(struct kvm_pmu *pmu, int pmc_idx)  in amd_pmu_get_pmc()  argument
30 	unsigned int num_counters = pmu->nr_arch_gp_counters;  in amd_pmu_get_pmc()
35 	return &pmu->gp_counters[array_index_nospec(pmc_idx, num_counters)];  in amd_pmu_get_pmc()
38 static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr,  in get_gp_pmc_amd()  argument
41 	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);  in get_gp_pmc_amd()
44 	if (!pmu->version)  in get_gp_pmc_amd()
52 		 * Each PMU counter has a pair of CTL and CTR MSRs. CTLn  in get_gp_pmc_amd()
73 	return amd_pmu_get_pmc(pmu, idx);  in get_gp_pmc_amd()
78 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_check_rdpmc_early()  local
80 	if (idx >= pmu->nr_arch_gp_counters)  in amd_check_rdpmc_early()
95 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_msr_idx_to_pmc()  local
98 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);  in amd_msr_idx_to_pmc()
99 	pmc = pmc ? pmc : get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);  in amd_msr_idx_to_pmc()
106 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_is_valid_msr()  local
110 		return pmu->version > 0;  in amd_is_valid_msr()
117 		return pmu->version > 1;  in amd_is_valid_msr()
120 		    msr < MSR_F15H_PERF_CTL0 + 2 * pmu->nr_arch_gp_counters)  in amd_is_valid_msr()
121 			return pmu->version > 1;  in amd_is_valid_msr()
130 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_pmu_get_msr()  local
135 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);  in amd_pmu_get_msr()
141 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);  in amd_pmu_get_msr()
152 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_pmu_set_msr()  local
158 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);  in amd_pmu_set_msr()
164 	pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);  in amd_pmu_set_msr()
166 		data &= ~pmu->reserved_bits;  in amd_pmu_set_msr()
179 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_pmu_refresh()  local
182 	pmu->version = 1;  in amd_pmu_refresh()
184 		pmu->version = 2;  in amd_pmu_refresh()
192 		pmu->nr_arch_gp_counters = ebx.split.num_core_pmc;  in amd_pmu_refresh()
194 		pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE;  in amd_pmu_refresh()
196 		pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS;  in amd_pmu_refresh()
199 	pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters,  in amd_pmu_refresh()
202 	if (pmu->version > 1) {  in amd_pmu_refresh()
203 		pmu->global_ctrl_rsvd = ~(BIT_ULL(pmu->nr_arch_gp_counters) - 1);  in amd_pmu_refresh()
204 		pmu->global_status_rsvd = pmu->global_ctrl_rsvd;  in amd_pmu_refresh()
207 	pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1;  in amd_pmu_refresh()
208 	pmu->reserved_bits = 0xfffffff000280000ull;  in amd_pmu_refresh()
209 	pmu->raw_event_mask = AMD64_RAW_EVENT_MASK;  in amd_pmu_refresh()
211 	pmu->counter_bitmask[KVM_PMC_FIXED] = 0;  in amd_pmu_refresh()
212 	pmu->nr_arch_fixed_counters = 0;  in amd_pmu_refresh()
217 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in amd_pmu_init()  local
223 		pmu->gp_counters[i].type = KVM_PMC_GP;  in amd_pmu_init()
224 		pmu->gp_counters[i].vcpu = vcpu;  in amd_pmu_init()
225 		pmu->gp_counters[i].idx = i;  in amd_pmu_init()
226 		pmu->gp_counters[i].current_config = 0;  in amd_pmu_init()