4  * Copyright (c) 2003-2004 Fabrice Bellard
45 	__acquires(&s->lock)  in pic_lock()
47 	spin_lock(&s->lock);  in pic_lock()
51 	__releases(&s->lock)  in pic_unlock()
53 	bool wakeup = s->wakeup_needed;  in pic_unlock()
57 	s->wakeup_needed = false;  in pic_unlock()
59 	spin_unlock(&s->lock);  in pic_unlock()
62 		kvm_for_each_vcpu(i, vcpu, s->kvm) {  in pic_unlock()
74 	s->isr &= ~(1 << irq);  in pic_clear_isr()
75 	if (s != &s->pics_state->pics[0])  in pic_clear_isr()
83 	pic_unlock(s->pics_state);  in pic_clear_isr()
84 	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);  in pic_clear_isr()
85 	pic_lock(s->pics_state);  in pic_clear_isr()
95 	if (s->elcr & mask)	/* level triggered */  in pic_set_irq1()
97 			ret = !(s->irr & mask);  in pic_set_irq1()
98 			s->irr |= mask;  in pic_set_irq1()
99 			s->last_irr |= mask;  in pic_set_irq1()
101 			s->irr &= ~mask;  in pic_set_irq1()
102 			s->last_irr &= ~mask;  in pic_set_irq1()
106 			if ((s->last_irr & mask) == 0) {  in pic_set_irq1()
107 				ret = !(s->irr & mask);  in pic_set_irq1()
108 				s->irr |= mask;  in pic_set_irq1()
110 			s->last_irr |= mask;  in pic_set_irq1()
112 			s->last_irr &= ~mask;  in pic_set_irq1()
114 	return (s->imr & mask) ? -1 : ret;  in pic_set_irq1()
127 	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)  in get_priority()
133  * return the pic wanted interrupt. return -1 if none
139 	mask = s->irr & ~s->imr;  in pic_get_irq()
142 		return -1;  in pic_get_irq()
148 	mask = s->isr;  in pic_get_irq()
149 	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])  in pic_get_irq()
156 		return (priority + s->priority_add) & 7;  in pic_get_irq()
158 		return -1;  in pic_get_irq()
169 	irq2 = pic_get_irq(&s->pics[1]);  in pic_update_irq()
174 		pic_set_irq1(&s->pics[0], 2, 1);  in pic_update_irq()
175 		pic_set_irq1(&s->pics[0], 2, 0);  in pic_update_irq()
177 	irq = pic_get_irq(&s->pics[0]);  in pic_update_irq()
178 	pic_irq_request(s->kvm, irq >= 0);  in pic_update_irq()
195 	irq_level = __kvm_irq_line_state(&s->irq_states[irq],  in kvm_pic_set_irq()
197 	ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);  in kvm_pic_set_irq()
199 	trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,  in kvm_pic_set_irq()
200 			      s->pics[irq >> 3].imr, ret == 0);  in kvm_pic_set_irq()
212 		__clear_bit(irq_source_id, &s->irq_states[i]);  in kvm_pic_clear_all()
221 	s->isr |= 1 << irq;  in pic_intack()
223 	 * We don't clear a level sensitive interrupt here  in pic_intack()
225 	if (!(s->elcr & (1 << irq)))  in pic_intack()
226 		s->irr &= ~(1 << irq);  in pic_intack()
228 	if (s->auto_eoi) {  in pic_intack()
229 		if (s->rotate_on_auto_eoi)  in pic_intack()
230 			s->priority_add = (irq + 1) & 7;  in pic_intack()
239 	struct kvm_pic *s = kvm->arch.vpic;  in kvm_pic_read_irq()
241 	s->output = 0;  in kvm_pic_read_irq()
244 	irq = pic_get_irq(&s->pics[0]);  in kvm_pic_read_irq()
246 		pic_intack(&s->pics[0], irq);  in kvm_pic_read_irq()
248 			irq2 = pic_get_irq(&s->pics[1]);  in kvm_pic_read_irq()
250 				pic_intack(&s->pics[1], irq2);  in kvm_pic_read_irq()
256 			intno = s->pics[1].irq_base + irq2;  in kvm_pic_read_irq()
258 			intno = s->pics[0].irq_base + irq;  in kvm_pic_read_irq()
264 		intno = s->pics[0].irq_base + irq;  in kvm_pic_read_irq()
277 	u8 edge_irr = s->irr & ~s->elcr;  in kvm_pic_reset()
280 	s->last_irr = 0;  in kvm_pic_reset()
281 	s->irr &= s->elcr;  in kvm_pic_reset()
282 	s->imr = 0;  in kvm_pic_reset()
283 	s->priority_add = 0;  in kvm_pic_reset()
284 	s->special_mask = 0;  in kvm_pic_reset()
285 	s->read_reg_select = 0;  in kvm_pic_reset()
286 	if (!s->init4) {  in kvm_pic_reset()
287 		s->special_fully_nested_mode = 0;  in kvm_pic_reset()
288 		s->auto_eoi = 0;  in kvm_pic_reset()
290 	s->init_state = 1;  in kvm_pic_reset()
292 	kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)  in kvm_pic_reset()
315 			s->init4 = val & 1;  in pic_ioport_write()
320 						"level sensitive irq not supported");  in pic_ioport_write()
324 				s->poll = 1;  in pic_ioport_write()
326 				s->read_reg_select = val & 1;  in pic_ioport_write()
328 				s->special_mask = (val >> 5) & 1;  in pic_ioport_write()
332 			case 0:  in pic_ioport_write()
333 			case 4:  in pic_ioport_write()
334 				s->rotate_on_auto_eoi = cmd >> 2;  in pic_ioport_write()
336 			case 1:	/* end of interrupt */  in pic_ioport_write()
337 			case 5:  in pic_ioport_write()
338 				priority = get_priority(s, s->isr);  in pic_ioport_write()
340 					irq = (priority + s->priority_add) & 7;  in pic_ioport_write()
342 						s->priority_add = (irq + 1) & 7;  in pic_ioport_write()
344 					pic_update_irq(s->pics_state);  in pic_ioport_write()
347 			case 3:  in pic_ioport_write()
350 				pic_update_irq(s->pics_state);  in pic_ioport_write()
352 			case 6:  in pic_ioport_write()
353 				s->priority_add = (val + 1) & 7;  in pic_ioport_write()
354 				pic_update_irq(s->pics_state);  in pic_ioport_write()
356 			case 7:  in pic_ioport_write()
358 				s->priority_add = (irq + 1) & 7;  in pic_ioport_write()
360 				pic_update_irq(s->pics_state);  in pic_ioport_write()
367 		switch (s->init_state) {  in pic_ioport_write()
368 		case 0: { /* normal mode */  in pic_ioport_write()
369 			u8 imr_diff = s->imr ^ val,  in pic_ioport_write()
370 				off = (s == &s->pics_state->pics[0]) ? 0 : 8;  in pic_ioport_write()
371 			s->imr = val;  in pic_ioport_write()
375 						s->pics_state->kvm,  in pic_ioport_write()
378 						!!(s->imr & (1 << irq)));  in pic_ioport_write()
379 			pic_update_irq(s->pics_state);  in pic_ioport_write()
382 		case 1:  in pic_ioport_write()
383 			s->irq_base = val & 0xf8;  in pic_ioport_write()
384 			s->init_state = 2;  in pic_ioport_write()
386 		case 2:  in pic_ioport_write()
387 			if (s->init4)  in pic_ioport_write()
388 				s->init_state = 3;  in pic_ioport_write()
390 				s->init_state = 0;  in pic_ioport_write()
392 		case 3:  in pic_ioport_write()
393 			s->special_fully_nested_mode = (val >> 4) & 1;  in pic_ioport_write()
394 			s->auto_eoi = (val >> 1) & 1;  in pic_ioport_write()
395 			s->init_state = 0;  in pic_ioport_write()
407 			s->pics_state->pics[0].isr &= ~(1 << 2);  in pic_poll_read()
408 			s->pics_state->pics[0].irr &= ~(1 << 2);  in pic_poll_read()
410 		s->irr &= ~(1 << ret);  in pic_poll_read()
413 			pic_update_irq(s->pics_state);  in pic_poll_read()
419 		pic_update_irq(s->pics_state);  in pic_poll_read()
430 	if (s->poll) {  in pic_ioport_read()
432 		s->poll = 0;  in pic_ioport_read()
435 			if (s->read_reg_select)  in pic_ioport_read()
436 				ret = s->isr;  in pic_ioport_read()
438 				ret = s->irr;  in pic_ioport_read()
440 			ret = s->imr;  in pic_ioport_read()
447 	s->elcr = val & s->elcr_mask;  in elcr_ioport_write()
453 	return s->elcr;  in elcr_ioport_read()
466 	case 0x20:  in picdev_write()
467 	case 0x21:  in picdev_write()
469 		pic_ioport_write(&s->pics[0], addr, data);  in picdev_write()
472 	case 0xa0:  in picdev_write()
473 	case 0xa1:  in picdev_write()
475 		pic_ioport_write(&s->pics[1], addr, data);  in picdev_write()
478 	case 0x4d0:  in picdev_write()
479 	case 0x4d1:  in picdev_write()
481 		elcr_ioport_write(&s->pics[addr & 1], data);  in picdev_write()
485 		return -EOPNOTSUPP;  in picdev_write()
501 	case 0x20:  in picdev_read()
502 	case 0x21:  in picdev_read()
503 	case 0xa0:  in picdev_read()
504 	case 0xa1:  in picdev_read()
506 		*data = pic_ioport_read(&s->pics[addr >> 7], addr);  in picdev_read()
509 	case 0x4d0:  in picdev_read()
510 	case 0x4d1:  in picdev_read()
512 		*data = elcr_ioport_read(&s->pics[addr & 1]);  in picdev_read()
516 		return -EOPNOTSUPP;  in picdev_read()
568 	struct kvm_pic *s = kvm->arch.vpic;  in pic_irq_request()
570 	if (!s->output)  in pic_irq_request()
571 		s->wakeup_needed = true;  in pic_irq_request()
572 	s->output = level;  in pic_irq_request()
597 		return -ENOMEM;  in kvm_pic_init()
598 	spin_lock_init(&s->lock);  in kvm_pic_init()
599 	s->kvm = kvm;  in kvm_pic_init()
600 	s->pics[0].elcr_mask = 0xf8;  in kvm_pic_init()
601 	s->pics[1].elcr_mask = 0xde;  in kvm_pic_init()
602 	s->pics[0].pics_state = s;  in kvm_pic_init()
603 	s->pics[1].pics_state = s;  in kvm_pic_init()
608 	kvm_iodevice_init(&s->dev_master, &picdev_master_ops);  in kvm_pic_init()
609 	kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);  in kvm_pic_init()
610 	kvm_iodevice_init(&s->dev_elcr, &picdev_elcr_ops);  in kvm_pic_init()
611 	mutex_lock(&kvm->slots_lock);  in kvm_pic_init()
613 				      &s->dev_master);  in kvm_pic_init()
617 	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);  in kvm_pic_init()
621 	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_elcr);  in kvm_pic_init()
625 	mutex_unlock(&kvm->slots_lock);  in kvm_pic_init()
627 	kvm->arch.vpic = s;  in kvm_pic_init()
632 	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);  in kvm_pic_init()
635 	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);  in kvm_pic_init()
638 	mutex_unlock(&kvm->slots_lock);  in kvm_pic_init()
647 	struct kvm_pic *vpic = kvm->arch.vpic;  in kvm_pic_destroy()
652 	mutex_lock(&kvm->slots_lock);  in kvm_pic_destroy()
653 	kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_master);  in kvm_pic_destroy()
654 	kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_slave);  in kvm_pic_destroy()
655 	kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_elcr);  in kvm_pic_destroy()
656 	mutex_unlock(&kvm->slots_lock);  in kvm_pic_destroy()
658 	kvm->arch.vpic = NULL;  in kvm_pic_destroy()