1 // SPDX-License-Identifier: GPL-2.0
8  * print a warning if not and turn off the TSC clock-source.
10  * The warp-check is point-to-point between two CPUs, the CPU
14  * Only two CPUs may participate - they can enter in any order.
63 	if (!resume && time_before(jiffies, adj->nextcheck))  in tsc_verify_tsc_adjust()
66 	adj->nextcheck = jiffies + HZ;  in tsc_verify_tsc_adjust()
69 	if (adj->adjusted == curval)  in tsc_verify_tsc_adjust()
73 	wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted);  in tsc_verify_tsc_adjust()
75 	if (!adj->warned || resume) {  in tsc_verify_tsc_adjust()
76 		pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",  in tsc_verify_tsc_adjust()
77 			smp_processor_id(), adj->adjusted, curval);  in tsc_verify_tsc_adjust()
78 		adj->warned = true;  in tsc_verify_tsc_adjust()
152 	cur->adjusted = bootval;  in tsc_sanitize_first_cpu()
169 	cur->bootval = bootval;  in tsc_store_and_check_tsc_adjust()
170 	cur->nextcheck = jiffies + HZ;  in tsc_store_and_check_tsc_adjust()
191 	cur->bootval = bootval;  in tsc_store_and_check_tsc_adjust()
192 	cur->nextcheck = jiffies + HZ;  in tsc_store_and_check_tsc_adjust()
193 	cur->warned = false;  in tsc_store_and_check_tsc_adjust()
198 	cur->adjusted = bootval;  in tsc_store_and_check_tsc_adjust()
221 	if (bootval != ref->bootval)  in tsc_store_and_check_tsc_adjust()
230 	if (bootval != ref->adjusted) {  in tsc_store_and_check_tsc_adjust()
231 		cur->adjusted = ref->adjusted;  in tsc_store_and_check_tsc_adjust()
232 		wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);  in tsc_store_and_check_tsc_adjust()
251  * we want to have the fastest, inlined, non-debug version
252  * of a critical section, to be able to prove TSC time-warps:
262  * TSC-warp measurement loop running on both CPUs.  This is not called
302 		 * we saw a time-warp of the TSC going backwards:  in check_tsc_warp()
306 			max_warp = max(max_warp, prev - now);  in check_tsc_warp()
319 	WARN(!(now-start),  in check_tsc_warp()
321 			now-start, end-start);  in check_tsc_warp()
326  * If the target CPU coming online doesn't have any of its core-siblings
327  * online, a timeout of 20msec will be used for the TSC-warp measurement
330  * have more and more logical-siblings in that socket).
333  * core-siblings, if the first logical CPU in a socket passed the sync test.
334  * But as the TSC is per-logical CPU and can potentially be modified wrongly
370 	while (atomic_read(&start_count) != cpus - 1)  in check_tsc_sync_source()
380 	while (atomic_read(&stop_count) != cpus-1)  in check_tsc_sync_source()
391 		pr_debug("TSC synchronization [CPU#%d -> CPU#%u]: passed\n",  in check_tsc_sync_source()
398 		pr_warn("TSC synchronization [CPU#%d -> CPU#%u]:\n",  in check_tsc_sync_source()
408 	 * Reset it - just in case we boot another CPU later:  in check_tsc_sync_source()
503 		cur_max_warp = -gbl_max_warp;  in check_tsc_sync_target()
514 	 * through a 3rd run for fine tuning.  in check_tsc_sync_target()
516 	cur->adjusted += cur_max_warp;  in check_tsc_sync_target()
519 		cpu, cur_max_warp, cur->adjusted);  in check_tsc_sync_target()
521 	wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted);  in check_tsc_sync_target()