Lines Matching +full:pll +full:- +full:clock +full:- +full:frequency

1 // SPDX-License-Identifier: GPL-2.0
3  * TSC frequency enumeration via MSR
14 #include <asm/intel-family.h>
19 #define MAX_NUM_FREQS	16 /* 4 bits to select the frequency */
22  * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
23  * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
25  * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
26  * unclear if the root PLL outputs are used directly by the CPU clock PLL or
27  * if there is another PLL in between.
28  * This does not matter though, we can model the chain of PLLs as a single PLL
30  * So we can create a simplified model of the CPU clock setup using a reference
31  * clock of 100 MHz plus a quotient which gets us as close to the frequency
54 	 * Some CPU frequencies in the SDM do not map to known PLL freqs, in
62  * Penwell and Clovertrail use spread spectrum clock,
79  * Bay Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
94  * Cherry Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
114  * Merriefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
125  * Moorefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
139  * Frequency step for Lightning Mountain SoC is fixed to 78 MHz,
140  * so all the frequency entries are 78000.
161  * MSR-based CPU/TSC frequency discovery for certain CPUs.
164  * Return processor base frequency in KHz, or 0 on failure.
179 	freq_desc = (struct freq_desc *)id->driver_data;
180 	if (freq_desc->use_msr_plat) {
190 	index = lo & freq_desc->mask;
191 	md = &freq_desc->muldiv[index];
197 	if (md->divider) {
198 		tscref = TSC_REFERENCE_KHZ * md->multiplier;
199 		freq = DIV_ROUND_CLOSEST(tscref, md->divider);
204 		res = DIV_ROUND_CLOSEST(tscref * ratio, md->divider);
206 		freq = freq_desc->freqs[index];
218 	 * TSC frequency determined by MSR is always considered "known"