Lines Matching full:100
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
84 * 100: 100 * 4 / 5 = 80.0000 MHz
95 * 0000: 100 * 5 / 6 = 83.3333 MHz
96 * 0001: 100 * 1 / 1 = 100.0000 MHz
97 * 0010: 100 * 4 / 3 = 133.3333 MHz
98 * 0011: 100 * 7 / 6 = 116.6667 MHz
99 * 0100: 100 * 4 / 5 = 80.0000 MHz
100 * 0101: 100 * 14 / 15 = 93.3333 MHz
101 * 0110: 100 * 9 / 10 = 90.0000 MHz
102 * 0111: 100 * 8 / 9 = 88.8889 MHz
103 * 1000: 100 * 7 / 8 = 87.5000 MHz
115 * 0001: 100 * 1 / 1 = 100.0000 MHz
116 * 0010: 100 * 4 / 3 = 133.3333 MHz
126 * 0000: 100 * 5 / 6 = 83.3333 MHz
127 * 0001: 100 * 1 / 1 = 100.0000 MHz
128 * 0010: 100 * 4 / 3 = 133.3333 MHz
129 * 0011: 100 * 1 / 1 = 100.0000 MHz