21 	 * E7520/E7320/E7525(revision ID 0x9 and below)  in quirk_intel_irqbalance()
25 	if (dev->revision > 0x9)  in quirk_intel_irqbalance()
29 	pci_read_config_byte(dev, 0xf4, &config);  in quirk_intel_irqbalance()
30 	pci_write_config_byte(dev, 0xf4, config|0x2);  in quirk_intel_irqbalance()
36 	pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);  in quirk_intel_irqbalance()
48 	if (!(config & 0x2))  in quirk_intel_irqbalance()
49 		pci_write_config_byte(dev, 0xf4, config);  in quirk_intel_irqbalance()
83 	val = readl(rcba_base + 0x3404);  in ich_force_hpet_resume()
84 	if (!(val & 0x80)) {  in ich_force_hpet_resume()
86 		writel(val | 0x80, rcba_base + 0x3404);  in ich_force_hpet_resume()
89 	val = readl(rcba_base + 0x3404);  in ich_force_hpet_resume()
90 	if (!(val & 0x80))  in ich_force_hpet_resume()
100 	int err = 0;  in ich_force_enable_hpet()
105 	pci_read_config_dword(dev, 0xF0, &rcba);  in ich_force_enable_hpet()
106 	rcba &= 0xFFFFC000;  in ich_force_enable_hpet()
107 	if (rcba == 0) {  in ich_force_enable_hpet()
114 	rcba_base = ioremap(rcba, 0x4000);  in ich_force_enable_hpet()
122 	val = readl(rcba_base + 0x3404);  in ich_force_enable_hpet()
124 	if (val & 0x80) {  in ich_force_enable_hpet()
126 		val = val & 0x3;  in ich_force_enable_hpet()
127 		force_hpet_address = 0xFED00000 | (val << 12);  in ich_force_enable_hpet()
129 			"0x%lx\n", force_hpet_address);  in ich_force_enable_hpet()
135 	writel(val | 0x80, rcba_base + 0x3404);  in ich_force_enable_hpet()
137 	val = readl(rcba_base + 0x3404);  in ich_force_enable_hpet()
138 	if (!(val & 0x80)) {  in ich_force_enable_hpet()
141 		val = val & 0x3;  in ich_force_enable_hpet()
142 		force_hpet_address = 0xFED00000 | (val << 12);  in ich_force_enable_hpet()
146 		force_hpet_address = 0;  in ich_force_enable_hpet()
153 			"0x%lx\n", force_hpet_address);  in ich_force_enable_hpet()
175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16,	/* ICH10 */
194 	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);  in old_ich_force_hpet_resume()
195 	gen_cntl &= (~(0x7 << 15));  in old_ich_force_hpet_resume()
196 	gen_cntl |= (0x4 << 15);  in old_ich_force_hpet_resume()
198 	pci_write_config_dword(cached_dev, 0xD0, gen_cntl);  in old_ich_force_hpet_resume()
199 	pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);  in old_ich_force_hpet_resume()
201 	val &= 0x7;  in old_ich_force_hpet_resume()
202 	if (val == 0x4)  in old_ich_force_hpet_resume()
216 	pci_read_config_dword(dev, 0xD0, &gen_cntl);  in old_ich_force_enable_hpet()
222 	val &= 0x7;  in old_ich_force_enable_hpet()
223 	if (val & 0x4) {  in old_ich_force_enable_hpet()
224 		val &= 0x3;  in old_ich_force_enable_hpet()
225 		force_hpet_address = 0xFED00000 | (val << 12);  in old_ich_force_enable_hpet()
226 		dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",  in old_ich_force_enable_hpet()
235 	gen_cntl &= (~(0x7 << 15));  in old_ich_force_enable_hpet()
236 	gen_cntl |= (0x4 << 15);  in old_ich_force_enable_hpet()
237 	pci_write_config_dword(dev, 0xD0, gen_cntl);  in old_ich_force_enable_hpet()
239 	pci_read_config_dword(dev, 0xD0, &gen_cntl);  in old_ich_force_enable_hpet()
242 	val &= 0x7;  in old_ich_force_enable_hpet()
243 	if (val & 0x4) {  in old_ich_force_enable_hpet()
245 		val &= 0x3;  in old_ich_force_enable_hpet()
246 		force_hpet_address = 0xFED00000 | (val << 12);  in old_ich_force_enable_hpet()
248 			"0x%lx\n", force_hpet_address);  in old_ich_force_enable_hpet()
290 	val = 0xfed00000 | 0x80;  in vt8237_force_hpet_resume()
291 	pci_write_config_dword(cached_dev, 0x68, val);  in vt8237_force_hpet_resume()
293 	pci_read_config_dword(cached_dev, 0x68, &val);  in vt8237_force_hpet_resume()
294 	if (val & 0x80)  in vt8237_force_hpet_resume()
312 	pci_read_config_dword(dev, 0x68, &val);  in vt8237_force_enable_hpet()
317 	if (val & 0x80) {  in vt8237_force_enable_hpet()
318 		force_hpet_address = (val & ~0x3ff);  in vt8237_force_enable_hpet()
319 		dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",  in vt8237_force_enable_hpet()
328 	val = 0xfed00000 | 0x80;  in vt8237_force_enable_hpet()
329 	pci_write_config_dword(dev, 0x68, val);  in vt8237_force_enable_hpet()
331 	pci_read_config_dword(dev, 0x68, &val);  in vt8237_force_enable_hpet()
332 	if (val & 0x80) {  in vt8237_force_enable_hpet()
333 		force_hpet_address = (val & ~0x3ff);  in vt8237_force_enable_hpet()
335 			"0x%lx\n", force_hpet_address);  in vt8237_force_enable_hpet()
353 	pci_write_config_dword(cached_dev, 0x14, 0xfed00000);  in ati_force_hpet_resume()
359 	int err = 0;  in ati_ixp4x0_rev()
360 	u32 d = 0;  in ati_ixp4x0_rev()
361 	u8  b = 0;  in ati_ixp4x0_rev()
363 	err = pci_read_config_byte(dev, 0xac, &b);  in ati_ixp4x0_rev()
365 	err |= pci_write_config_byte(dev, 0xac, b);  in ati_ixp4x0_rev()
366 	err |= pci_read_config_dword(dev, 0x70, &d);  in ati_ixp4x0_rev()
368 	err |= pci_write_config_dword(dev, 0x70, d);  in ati_ixp4x0_rev()
369 	err |= pci_read_config_dword(dev, 0x8, &d);  in ati_ixp4x0_rev()
370 	d &= 0xff;  in ati_ixp4x0_rev()
371 	dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);  in ati_ixp4x0_rev()
392 	if (d  < 0x82)  in ati_force_enable_hpet()
396 	pci_write_config_dword(dev, 0x14, 0xfed00000);  in ati_force_enable_hpet()
397 	pci_read_config_dword(dev, 0x14, &val);  in ati_force_enable_hpet()
400 	outb(0x72, 0xcd6); b = inb(0xcd7);  in ati_force_enable_hpet()
401 	b |= 0x1;  in ati_force_enable_hpet()
402 	outb(0x72, 0xcd6); outb(b, 0xcd7);  in ati_force_enable_hpet()
403 	outb(0x72, 0xcd6); b = inb(0xcd7);  in ati_force_enable_hpet()
404 	if (!(b & 0x1))  in ati_force_enable_hpet()
406 	pci_read_config_dword(dev, 0x64, &d);  in ati_force_enable_hpet()
408 	pci_write_config_dword(dev, 0x64, d);  in ati_force_enable_hpet()
409 	pci_read_config_dword(dev, 0x64, &d);  in ati_force_enable_hpet()
415 	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",  in ati_force_enable_hpet()
427 	pci_write_config_dword(cached_dev, 0x44, 0xfed00001);  in nvidia_force_hpet_resume()
443 	pci_write_config_dword(dev, 0x44, 0xfed00001);  in nvidia_force_enable_hpet()
444 	pci_read_config_dword(dev, 0x44, &val);  in nvidia_force_enable_hpet()
445 	force_hpet_address = val & 0xfffffffe;  in nvidia_force_enable_hpet()
447 	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",  in nvidia_force_enable_hpet()
453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
503  * 0xfed00000
510 	force_hpet_address = 0xFED00000;  in e6xx_force_enable_hpet()
513 		"0x%lx\n", force_hpet_address);  in e6xx_force_enable_hpet()
544 	devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);  in quirk_amd_nb_node()
549 	pci_read_config_dword(nb_ht, 0x60, &val);  in quirk_amd_nb_node()
599  * applies to Fam16h models 00h-0Fh
601  * See "Revision Guide" for AMD F16h models 00h-0fh,
610 	 * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b  in amd_disable_seq_and_redirect_scrub()
612 	pci_read_config_dword(dev, 0x58, &val);  in amd_disable_seq_and_redirect_scrub()
613 	if (val & 0x1F) {  in amd_disable_seq_and_redirect_scrub()
614 		val &= ~(0x1F);  in amd_disable_seq_and_redirect_scrub()
615 		pci_write_config_dword(dev, 0x58, val);  in amd_disable_seq_and_redirect_scrub()
618 	pci_read_config_dword(dev, 0x5C, &val);  in amd_disable_seq_and_redirect_scrub()
619 	if (val & BIT(0)) {  in amd_disable_seq_and_redirect_scrub()
620 		val &= ~BIT(0);  in amd_disable_seq_and_redirect_scrub()
621 		pci_write_config_dword(dev, 0x5c, val);  in amd_disable_seq_and_redirect_scrub()
633 	pci_read_config_dword(pdev, 0x84, &capid0);  in quirk_intel_brickland_xeon_ras_cap()
635 	if (capid0 & 0x10)  in quirk_intel_brickland_xeon_ras_cap()
644 	pci_read_config_dword(pdev, 0x84, &capid0);  in quirk_intel_purley_xeon_ras_cap()
645 	pci_read_config_dword(pdev, 0x98, &capid5);  in quirk_intel_purley_xeon_ras_cap()
652 	if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0))  in quirk_intel_purley_xeon_ras_cap()
656 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3, quirk_intel_brickland_xeon_ras_cap);
657 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ras_cap);
658 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, quirk_intel_brickland_xeon_ras_cap);
659 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2083, quirk_intel_purley_xeon_ras_cap);