Lines Matching +full:cpu +full:- +full:cfg
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/cpu.h>
29 unsigned int cpu; member
134 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
144 u32 i, id, period, cfg, status, channels, l, h; in _hpet_print_config() local
152 cfg = hpet_readl(HPET_CFG); in _hpet_print_config()
154 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); in _hpet_print_config()
211 hd.hd_irq[i] = hc->irq; in hpet_reserve_platform_timers()
213 switch (hc->mode) { in hpet_reserve_platform_timers()
216 hc->mode = HPET_MODE_DEVICE; in hpet_reserve_platform_timers()
220 hpet_reserve_timer(&hd, hc->num); in hpet_reserve_platform_timers()
236 if (hc->mode == HPET_MODE_UNUSED) { in hpet_select_device_channel()
237 hc->mode = HPET_MODE_DEVICE; in hpet_select_device_channel()
251 u32 cfg = hpet_readl(HPET_CFG); in hpet_stop_counter() local
253 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
254 hpet_writel(cfg, HPET_CFG); in hpet_stop_counter()
265 unsigned int cfg = hpet_readl(HPET_CFG); in hpet_start_counter() local
267 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
268 hpet_writel(cfg, HPET_CFG); in hpet_start_counter()
291 unsigned int cfg = hpet_readl(HPET_CFG); in hpet_enable_legacy_int() local
293 cfg |= HPET_CFG_LEGACY; in hpet_enable_legacy_int()
294 hpet_writel(cfg, HPET_CFG); in hpet_enable_legacy_int()
300 unsigned int channel = clockevent_to_channel(evt)->num; in hpet_clkevt_set_state_periodic()
301 unsigned int cfg, cmp, now; in hpet_clkevt_set_state_periodic() local
305 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult; in hpet_clkevt_set_state_periodic()
306 delta >>= evt->shift; in hpet_clkevt_set_state_periodic()
309 cfg = hpet_readl(HPET_Tn_CFG(channel)); in hpet_clkevt_set_state_periodic()
310 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | in hpet_clkevt_set_state_periodic()
312 hpet_writel(cfg, HPET_Tn_CFG(channel)); in hpet_clkevt_set_state_periodic()
319 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, in hpet_clkevt_set_state_periodic()
331 unsigned int channel = clockevent_to_channel(evt)->num; in hpet_clkevt_set_state_oneshot()
332 unsigned int cfg; in hpet_clkevt_set_state_oneshot() local
334 cfg = hpet_readl(HPET_Tn_CFG(channel)); in hpet_clkevt_set_state_oneshot()
335 cfg &= ~HPET_TN_PERIODIC; in hpet_clkevt_set_state_oneshot()
336 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; in hpet_clkevt_set_state_oneshot()
337 hpet_writel(cfg, HPET_Tn_CFG(channel)); in hpet_clkevt_set_state_oneshot()
344 unsigned int channel = clockevent_to_channel(evt)->num; in hpet_clkevt_set_state_shutdown()
345 unsigned int cfg; in hpet_clkevt_set_state_shutdown() local
347 cfg = hpet_readl(HPET_Tn_CFG(channel)); in hpet_clkevt_set_state_shutdown()
348 cfg &= ~HPET_TN_ENABLE; in hpet_clkevt_set_state_shutdown()
349 hpet_writel(cfg, HPET_Tn_CFG(channel)); in hpet_clkevt_set_state_shutdown()
364 unsigned int channel = clockevent_to_channel(evt)->num; in hpet_clkevt_set_next_event()
394 res = (s32)(cnt - hpet_readl(HPET_COUNTER)); in hpet_clkevt_set_next_event()
396 return res < HPET_MIN_CYCLES ? -ETIME : 0; in hpet_clkevt_set_next_event()
401 struct clock_event_device *evt = &hc->evt; in hpet_init_clockevent()
403 evt->rating = rating; in hpet_init_clockevent()
404 evt->irq = hc->irq; in hpet_init_clockevent()
405 evt->name = hc->name; in hpet_init_clockevent()
406 evt->cpumask = cpumask_of(hc->cpu); in hpet_init_clockevent()
407 evt->set_state_oneshot = hpet_clkevt_set_state_oneshot; in hpet_init_clockevent()
408 evt->set_next_event = hpet_clkevt_set_next_event; in hpet_init_clockevent()
409 evt->set_state_shutdown = hpet_clkevt_set_state_shutdown; in hpet_init_clockevent()
411 evt->features = CLOCK_EVT_FEAT_ONESHOT; in hpet_init_clockevent()
412 if (hc->boot_cfg & HPET_TN_PERIODIC) { in hpet_init_clockevent()
413 evt->features |= CLOCK_EVT_FEAT_PERIODIC; in hpet_init_clockevent()
414 evt->set_state_periodic = hpet_clkevt_set_state_periodic; in hpet_init_clockevent()
421 * Start HPET with the boot CPU's cpumask and make it global after in hpet_legacy_clockevent_register()
424 hc->cpu = boot_cpu_data.cpu_index; in hpet_legacy_clockevent_register()
425 strscpy(hc->name, "hpet", sizeof(hc->name)); in hpet_legacy_clockevent_register()
428 hc->evt.tick_resume = hpet_clkevt_legacy_resume; in hpet_legacy_clockevent_register()
458 hc->evt.features |= CLOCK_EVT_FEAT_PERIODIC; in hpet_legacy_clockevent_register()
459 hc->evt.set_state_periodic = hpet_clkevt_set_state_periodic; in hpet_legacy_clockevent_register()
464 clockevents_config_and_register(&hc->evt, hpet_freq, in hpet_legacy_clockevent_register()
466 global_clock_event = &hc->evt; in hpet_legacy_clockevent_register()
477 unsigned int cfg; in hpet_msi_unmask() local
479 cfg = hpet_readl(HPET_Tn_CFG(hc->num)); in hpet_msi_unmask()
480 cfg |= HPET_TN_ENABLE | HPET_TN_FSB; in hpet_msi_unmask()
481 hpet_writel(cfg, HPET_Tn_CFG(hc->num)); in hpet_msi_unmask()
487 unsigned int cfg; in hpet_msi_mask() local
489 cfg = hpet_readl(HPET_Tn_CFG(hc->num)); in hpet_msi_mask()
490 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); in hpet_msi_mask()
491 hpet_writel(cfg, HPET_Tn_CFG(hc->num)); in hpet_msi_mask()
496 hpet_writel(msg->data, HPET_Tn_ROUTE(hc->num)); in hpet_msi_write()
497 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hc->num) + 4); in hpet_msi_write()
506 .name = "HPET-MSI",
520 irq_domain_set_info(domain, virq, arg->hwirq, info->chip, NULL, in hpet_msi_init()
521 handle_edge_irq, arg->data, "edge"); in hpet_msi_init()
551 domain_info->data = (void *)(long)hpet_id; in hpet_create_irq_domain()
571 hpet_msi_controller.name = "IR-HPET-MSI"; in hpet_create_irq_domain()
585 return (int)(long)info->data; in hpet_dev_id()
605 struct irq_data *data = irq_get_irq_data(hc->irq); in hpet_clkevt_msi_resume()
618 struct clock_event_device *evt = &hc->evt; in hpet_msi_interrupt_handler()
620 if (!evt->event_handler) { in hpet_msi_interrupt_handler()
621 pr_info("Spurious interrupt HPET channel %d\n", hc->num); in hpet_msi_interrupt_handler()
625 evt->event_handler(evt); in hpet_msi_interrupt_handler()
631 if (request_irq(hc->irq, hpet_msi_interrupt_handler, in hpet_setup_msi_irq()
633 hc->name, hc)) in hpet_setup_msi_irq()
634 return -1; in hpet_setup_msi_irq()
636 disable_irq(hc->irq); in hpet_setup_msi_irq()
637 irq_set_affinity(hc->irq, cpumask_of(hc->cpu)); in hpet_setup_msi_irq()
638 enable_irq(hc->irq); in hpet_setup_msi_irq()
640 pr_debug("%s irq %u for MSI\n", hc->name, hc->irq); in hpet_setup_msi_irq()
645 /* Invoked from the hotplug callback on @cpu */
646 static void init_one_hpet_msi_clockevent(struct hpet_channel *hc, int cpu) in init_one_hpet_msi_clockevent() argument
648 struct clock_event_device *evt = &hc->evt; in init_one_hpet_msi_clockevent()
650 hc->cpu = cpu; in init_one_hpet_msi_clockevent()
651 per_cpu(cpu_hpet_channel, cpu) = hc; in init_one_hpet_msi_clockevent()
655 evt->tick_resume = hpet_clkevt_msi_resume; in init_one_hpet_msi_clockevent()
668 if (hc->mode != HPET_MODE_CLOCKEVT || hc->in_use) in hpet_get_unused_clockevent()
670 hc->in_use = 1; in hpet_get_unused_clockevent()
676 static int hpet_cpuhp_online(unsigned int cpu) in hpet_cpuhp_online() argument
681 init_one_hpet_msi_clockevent(hc, cpu); in hpet_cpuhp_online()
685 static int hpet_cpuhp_dead(unsigned int cpu) in hpet_cpuhp_dead() argument
687 struct hpet_channel *hc = per_cpu(cpu_hpet_channel, cpu); in hpet_cpuhp_dead()
691 free_irq(hc->irq, hc); in hpet_cpuhp_dead()
692 hc->in_use = 0; in hpet_cpuhp_dead()
693 per_cpu(cpu_hpet_channel, cpu) = NULL; in hpet_cpuhp_dead()
703 /* No point if MSI is disabled or CPU has an Always Running APIC Timer */ in hpet_select_clockevents()
717 if (hc->mode != HPET_MODE_UNUSED) in hpet_select_clockevents()
721 if (!(hc->boot_cfg & HPET_TN_FSB_CAP)) in hpet_select_clockevents()
724 sprintf(hc->name, "hpet%d", i); in hpet_select_clockevents()
726 irq = hpet_assign_irq(hpet_domain, hc, hc->num); in hpet_select_clockevents()
730 hc->irq = irq; in hpet_select_clockevents()
731 hc->mode = HPET_MODE_CLOCKEVT; in hpet_select_clockevents()
737 pr_info("%d channels of %d reserved for per-cpu timers\n", in hpet_select_clockevents()
765 * other CPUs can use the counter value read by the first CPU in the group.
767 * This special feature is only enabled on x86-64 systems. It is unlikely
768 * that 32-bit x86 systems will have enough CPUs to require this feature
769 * with its associated locking overhead. We also need 64-bit atomic read.
772 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
824 * -------------- in read_hpet()
826 * its value is up-to-date. in read_hpet()
843 * For UP or 32-bit.
867 * config register reads a non-0xffffffff value to make sure that the
870 * A counting loop is safe, as the HPET access takes thousands of CPU cycles.
872 * On non-SB700 based machines this check is only done once and has no
907 } while ((now - start) < 200000UL); in hpet_counting()
935 * - ACPI tables
936 * - Enablement of intel_idle
937 * - Command line arguments which limit intel_idle C-state support
941 * fact that it is impossible to reliably query TSC and CPU frequency via
951 * dysfunctional in deeper C-states.
955 * and per CPU timer interrupts.
972 /* Check whether PC10 is enabled in PKG C-state limit */ in hpet_is_pc10_damaged()
988 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
992 u32 hpet_period, cfg, id, irq; in hpet_enable() local
1049 cfg = hpet_readl(HPET_CFG); in hpet_enable()
1050 hpet_base.boot_cfg = cfg; in hpet_enable()
1051 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); in hpet_enable()
1052 hpet_writel(cfg, HPET_CFG); in hpet_enable()
1053 if (cfg) in hpet_enable()
1054 pr_warn("Global config: Unknown bits %#x\n", cfg); in hpet_enable()
1058 hc->num = i; in hpet_enable()
1060 cfg = hpet_readl(HPET_Tn_CFG(i)); in hpet_enable()
1061 hc->boot_cfg = cfg; in hpet_enable()
1062 irq = (cfg & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; in hpet_enable()
1063 hc->irq = irq; in hpet_enable()
1065 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); in hpet_enable()
1066 hpet_writel(cfg, HPET_Tn_CFG(i)); in hpet_enable()
1068 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP in hpet_enable()
1071 if (cfg) in hpet_enable()
1072 pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg); in hpet_enable()
1116 * 2) Reserve up to num_possible_cpus() channels as per CPU clockevents
1126 return -ENODEV; in hpet_late_init()
1133 return -ENODEV; in hpet_late_init()
1162 u32 cfg; in hpet_disable() local
1168 cfg = hpet_base.boot_cfg; in hpet_disable()
1169 cfg &= ~HPET_CFG_ENABLE; in hpet_disable()
1170 hpet_writel(cfg, HPET_CFG); in hpet_disable()
1189 * 1) Update Interrupt - generate an interrupt, every second, when the
1191 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1192 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1193 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all frequencies in powers of 2)
1226 return (s32)(c2 - c1) < 0; in hpet_cnt_ahead()
1235 return -ENODEV; in hpet_register_irq_handler()
1237 return -EBUSY; in hpet_register_irq_handler()
1267 unsigned int cfg, cnt, delta; in hpet_rtc_timer_init() local
1277 clc = (uint64_t) evt->mult * NSEC_PER_SEC; in hpet_rtc_timer_init()
1278 clc >>= evt->shift + DEFAULT_RTC_SHIFT; in hpet_rtc_timer_init()
1293 cfg = hpet_readl(HPET_T1_CFG); in hpet_rtc_timer_init()
1294 cfg &= ~HPET_TN_PERIODIC; in hpet_rtc_timer_init()
1295 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; in hpet_rtc_timer_init()
1296 hpet_writel(cfg, HPET_T1_CFG); in hpet_rtc_timer_init()
1306 u32 cfg = hpet_readl(HPET_T1_CFG); in hpet_disable_rtc_channel() local
1308 cfg &= ~HPET_TN_ENABLE; in hpet_disable_rtc_channel()
1309 hpet_writel(cfg, HPET_T1_CFG); in hpet_disable_rtc_channel()
1340 hpet_prev_update_sec = -1; in hpet_set_rtc_irq_bit()
1374 clc = (uint64_t) evt->mult * NSEC_PER_SEC; in hpet_set_periodic_freq()
1376 clc >>= evt->shift; in hpet_set_periodic_freq()
1388 int lost_ints = -1; in hpet_rtc_timer_reinit()