131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)  in smca_get_bank_type()  argument
135 	if (bank >= MAX_NR_BANKS)  in smca_get_bank_type()
138 	b = &per_cpu(smca_banks, cpu)[bank];  in smca_get_bank_type()
212  * So to define a unique name for each bank, we use a temp c-string to append
222 	/* This block's number within its bank. */
224 	/* MCA bank number that contains this block. */
225 	unsigned int		bank;  member
226 	/* CPU which controls this block's MCA bank. */
232 	/* Bank can generate an interrupt. */
238 	/* List of threshold blocks within this block's MCA bank. */
244 	/* List of threshold blocks within this MCA bank. */
265 static void smca_configure(unsigned int bank, unsigned int cpu)  in smca_configure()  argument
271 	u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);  in smca_configure()
278 		 * bank. It also means that the OS will configure deferred  in smca_configure()
287 		 * SMCA sets the Deferred Error Interrupt type per bank.  in smca_configure()
300 		this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));  in smca_configure()
305 	if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {  in smca_configure()
306 		pr_warn("Failed to read MCA_IPID for bank %d\n", bank);  in smca_configure()
317 			this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;  in smca_configure()
318 			this_cpu_ptr(smca_banks)[bank].id = low;  in smca_configure()
319 			this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;  in smca_configure()
352 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)  in lvt_interrupt_supported()  argument
355 	 * bank 4 supports APIC LVT interrupts implicitly since forever.  in lvt_interrupt_supported()
357 	if (bank == 4)  in lvt_interrupt_supported()
362 	 * bank can generate APIC LVT interrupts  in lvt_interrupt_supported()
373 		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,  in lvt_off_valid()
374 		       b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
388 		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n",  in lvt_off_valid()
389 		       b->cpu, apic, b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
503 			     unsigned int bank, unsigned int block,  in get_block_address()  argument
508 	if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))  in get_block_address()
513 			return MSR_AMD64_SMCA_MCx_MISC(bank);  in get_block_address()
518 		return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);  in get_block_address()
524 		addr = mca_msr_reg(bank, MCA_MISC);  in get_block_address()
538 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,  in prepare_threshold_block()  argument
547 		per_cpu(bank_map, cpu) |= BIT_ULL(bank);  in prepare_threshold_block()
551 	b.bank			= bank;  in prepare_threshold_block()
554 	b.interrupt_capable	= lvt_interrupt_supported(bank, misc_high);  in prepare_threshold_block()
586 	enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);  in amd_filter_mce()
597 		if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)  in amd_filter_mce()
607  * - Prevent possible spurious interrupts from the IF bank on Family 0x17
610 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)  in disable_err_thresholding()  argument
617 	if (c->x86 == 0x15 && bank == 4) {  in disable_err_thresholding()
624 		if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF)  in disable_err_thresholding()
627 		msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);  in disable_err_thresholding()
664 	 * Various K7s with broken bank 0 around. Always disable  in amd_apply_cpu_quirks()
674 	unsigned int bank, block, cpu = smp_processor_id();  in mce_amd_feature_init()  local
682 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {  in mce_amd_feature_init()
684 			smca_configure(bank, cpu);  in mce_amd_feature_init()
686 		disable_err_thresholding(c, bank);  in mce_amd_feature_init()
689 			address = get_block_address(address, low, high, bank, block, cpu);  in mce_amd_feature_init()
703 			offset = prepare_threshold_block(bank, block, address, offset, high);  in mce_amd_feature_init()
718  * DRAM ECC errors are reported in the Northbridge (bank 4) with
723 	return m->bank == 4 && XEC(m->status, 0x1f) == 8;  in legacy_mce_is_memory_error()
737 	bank_type = smca_get_bank_type(m->extcpu, m->bank);  in smca_mce_is_memory_error()
759  *	   northbridge (bank 4).
764  *	a) Reported in legacy bank 4 with extended error code (XEC) 8.
765  *	b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore,
776 		else if (m->bank == 4)  in amd_mce_usable_address()
780 	/* Check poison bit for all other bank types. */  in amd_mce_usable_address()
788 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)  in __log_error()  argument
797 	m->bank   = bank;  in __log_error()
807 		rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid);  in __log_error()
810 			rdmsrq(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd);  in __log_error()
811 			rdmsrq(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1);  in __log_error()
812 			rdmsrq(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2);  in __log_error()
832 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)  in _log_error_bank()  argument
843 	__log_error(bank, status, addr, misc);  in _log_error_bank()
850 static bool _log_error_deferred(unsigned int bank, u32 misc)  in _log_error_deferred()  argument
852 	if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS),  in _log_error_deferred()
853 			     mca_msr_reg(bank, MCA_ADDR), misc))  in _log_error_deferred()
864 	wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);  in _log_error_deferred()
877 static void log_error_deferred(unsigned int bank)  in log_error_deferred()  argument
879 	if (_log_error_deferred(bank, 0))  in log_error_deferred()
886 	_log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),  in log_error_deferred()
887 			      MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);  in log_error_deferred()
893 	unsigned int bank;  in amd_deferred_error_interrupt()  local
895 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank)  in amd_deferred_error_interrupt()
896 		log_error_deferred(bank);  in amd_deferred_error_interrupt()
899 static void log_error_thresholding(unsigned int bank, u64 misc)  in log_error_thresholding()  argument
901 	_log_error_deferred(bank, misc);  in log_error_thresholding()
919 	log_error_thresholding(block->bank, ((u64)high << 32) | low);  in log_and_reset_block()
934 	unsigned int bank, cpu = smp_processor_id();  in amd_threshold_interrupt()  local
938 	 * Validate that the threshold bank has been initialized already. The  in amd_threshold_interrupt()
945 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {  in amd_threshold_interrupt()
946 		if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank)))  in amd_threshold_interrupt()
949 		thr_bank = bp[bank];  in amd_threshold_interrupt()
960 	mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);  in amd_clear_bank()
1103 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b)  in get_name()  argument
1108 		if (b && bank == 4)  in get_name()
1111 		return th_names[bank];  in get_name()
1114 	bank_type = smca_get_bank_type(cpu, bank);  in get_name()
1127 		snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_bank_%u", bank);  in get_name()
1136 			  per_cpu(smca_banks, cpu)[bank].sysfs_id);  in get_name()
1141 				     unsigned int bank, unsigned int block,  in allocate_threshold_blocks()  argument
1148 	if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))  in allocate_threshold_blocks()
1170 	b->bank			= bank;  in allocate_threshold_blocks()
1174 	b->interrupt_capable	= lvt_interrupt_supported(bank, high);  in allocate_threshold_blocks()
1186 	err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));  in allocate_threshold_blocks()
1190 	address = get_block_address(address, low, high, bank, ++block, cpu);  in allocate_threshold_blocks()
1194 	err = allocate_threshold_blocks(cpu, tb, bank, block, address);  in allocate_threshold_blocks()
1212 				 unsigned int bank)  in threshold_create_bank()  argument
1216 	const char *name = get_name(cpu, bank, NULL);  in threshold_create_bank()
1228 	/* Associate the bank with the per-CPU MCE device */  in threshold_create_bank()
1237 	err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));  in threshold_create_bank()
1241 	bp[bank] = b;  in threshold_create_bank()
1257 static void threshold_remove_bank(struct threshold_bank *bank)  in threshold_remove_bank()  argument
1261 	list_for_each_entry_safe(pos, tmp, &bank->miscj, miscj) {  in threshold_remove_bank()
1266 	kobject_put(bank->kobj);  in threshold_remove_bank()
1267 	kfree(bank);  in threshold_remove_bank()
1272 	unsigned int bank, numbanks = this_cpu_read(mce_num_banks);  in __threshold_remove_device()  local
1274 	for (bank = 0; bank < numbanks; bank++) {  in __threshold_remove_device()
1275 		if (!bp[bank])  in __threshold_remove_device()
1278 		threshold_remove_bank(bp[bank]);  in __threshold_remove_device()
1279 		bp[bank] = NULL;  in __threshold_remove_device()
1314 	unsigned int numbanks, bank;  in mce_threshold_create_device()  local
1329 	for (bank = 0; bank < numbanks; ++bank) {  in mce_threshold_create_device()
1330 		if (!(this_cpu_read(bank_map) & BIT_ULL(bank)))  in mce_threshold_create_device()
1332 		if (threshold_create_bank(bp, cpu, bank)) {  in mce_threshold_create_device()