1 // SPDX-License-Identifier: GPL-2.0
18 #include <asm/intel-family.h>
39  * Processors which have self-snooping capability can handle conflicting
47 	switch (c->x86_vfm) {  in check_memory_type_self_snoop_errata()
79 	if (c->x86 != 6)  in probe_xeon_phi_r3mwait()
81 	switch (c->x86_vfm) {  in probe_xeon_phi_r3mwait()
103  * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
104  * - https://kb.vmware.com/s/article/52345
105  * - Microcode revisions observed in the wild
106  * - Release note from 20180108 microcode release
149 		if (c->x86_vfm == spectre_bad_microcodes[i].vfm &&  in bad_spectre_microcode()
150 		    c->x86_stepping == spectre_bad_microcodes[i].stepping)  in bad_spectre_microcode()
151 			return (c->microcode <= spectre_bad_microcodes[i].microcode);  in bad_spectre_microcode()
188 	c->x86_phys_bits -= keyid_bits;  in detect_tme_early()
198 	if (c->x86 < 6 || (c->x86 == 6 && c->x86_model < 0xd))  in intel_unlock_cpuid_leafs()
206 		c->cpuid_level = cpuid_eax(0);  in intel_unlock_cpuid_leafs()
213 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||  in early_init_intel()
214 		(c->x86 == 0x6 && c->x86_model >= 0x0e))  in early_init_intel()
217 	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))  in early_init_intel()
218 		c->microcode = intel_get_microcode_revision();  in early_init_intel()
244 	if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 &&  in early_init_intel()
245 	    c->microcode < 0x20e) {  in early_init_intel()
254 	if (c->x86 == 15 && c->x86_cache_alignment == 64)  in early_init_intel()
255 		c->x86_cache_alignment = 128;  in early_init_intel()
259 	if (c->x86 == 0xF && c->x86_model == 0x3  in early_init_intel()
260 	    && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))  in early_init_intel()
261 		c->x86_phys_bits = 36;  in early_init_intel()
264 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate  in early_init_intel()
265 	 * with P/T states and does not stop in deep C-states.  in early_init_intel()
268 	 * cabinets - we turn it off in that case explicitly.)  in early_init_intel()
270 	if (c->x86_power & (1 << 8)) {  in early_init_intel()
276 	switch (c->x86_vfm) {  in early_init_intel()
296 	if (c->x86_vfm >= INTEL_PENTIUM_PRO &&  in early_init_intel()
297 	    c->x86_vfm <= INTEL_CORE_YONAH)  in early_init_intel()
304 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
323 	if (c->x86_vfm == INTEL_QUARK_X1000) {  in early_init_intel()
366 	if (!c->cpu_index)  in intel_smp_check()
372 	if (c->x86 == 5 &&  in intel_smp_check()
373 	    c->x86_stepping >= 1 && c->x86_stepping <= 4 &&  in intel_smp_check()
374 	    c->x86_model <= 3) {  in intel_smp_check()
401 	if (c->x86 == 5 && c->x86_model < 9) {  in intel_workarounds()
406 			pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");  in intel_workarounds()
416 	if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)  in intel_workarounds()
434 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {  in intel_workarounds()
448 	if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&  in intel_workarounds()
449 	    (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))  in intel_workarounds()
457 	switch (c->x86) {  in intel_workarounds()
458 	case 4:		/* 486: untested */  in intel_workarounds()
462 	case 6:		/* PII/PIII only like movsl with 8-byte alignment */  in intel_workarounds()
465 	case 15:	/* P4 is OK down to 8-byte alignment */  in intel_workarounds()
532 	if (c->cpuid_level > 9) {  in init_intel()
553 	    (c->x86_vfm == INTEL_CORE2_DUNNINGTON ||  in init_intel()
554 	     c->x86_vfm == INTEL_NEHALEM_EX ||  in init_intel()
555 	     c->x86_vfm == INTEL_WESTMERE_EX))  in init_intel()
559 	    (c->x86_vfm == INTEL_ATOM_GOLDMONT ||  in init_intel()
560 	     c->x86_vfm == INTEL_LUNARLAKE_M))  in init_intel()
564 	if (c->x86 == 15)  in init_intel()
565 		c->x86_cache_alignment = c->x86_clflush_size * 2;  in init_intel()
566 	if (c->x86 == 6)  in init_intel()
574 	if (c->x86 == 6) {  in init_intel()
575 		unsigned int l2 = c->x86_cache_size;  in init_intel()
578 		switch (c->x86_model) {  in init_intel()
589 			else if (c->x86_stepping == 0 || c->x86_stepping == 5)  in init_intel()
590 				p = "Celeron-A";  in init_intel()
600 			strcpy(c->x86_model_id, p);  in init_intel()
621 	 * One has 256kb of cache, the other 512. We have no way  in intel_size_cache()
625 	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))  in intel_size_cache()
629 	 * Intel Quark SoC X1000 contains a 4-way set associative  in intel_size_cache()
632 	if ((c->x86 == 5) && (c->x86_model == 9))  in intel_size_cache()
661  * All of leaf 0x2's one-byte TLB descriptors implies the same number of
663  * exception: it implies 4 dTLB entries for 1GB pages 32 dTLB entries
664  * for 2MB or 4MB pages.  Encode descriptor 0x63 dTLB entry count for
665  * 2MB/4MB pages here, as its count for dTLB 1GB pages is already at the
671 	{ 0x01, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages, 4-way set associative" },
672 	{ 0x02, TLB_INST_4M,		2,	" TLB_INST 4 MByte pages, full associative" },
673 	{ 0x03, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way set associative" },
674 	{ 0x04, TLB_DATA_4M,		8,	" TLB_DATA 4 MByte pages, 4-way set associative" },
675 	{ 0x05, TLB_DATA_4M,		32,	" TLB_DATA 4 MByte pages, 4-way set associative" },
676 	{ 0x0b, TLB_INST_4M,		4,	" TLB_INST 4 MByte pages, 4-way set associative" },
677 	{ 0x4f, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages" },
678 	{ 0x50, TLB_INST_ALL,		64,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
679 	{ 0x51, TLB_INST_ALL,		128,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
680 	{ 0x52, TLB_INST_ALL,		256,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
681 	{ 0x55, TLB_INST_2M_4M,		7,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
682 	{ 0x56, TLB_DATA0_4M,		16,	" TLB_DATA0 4 MByte pages, 4-way set associative" },
683 	{ 0x57, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, 4-way associative" },
684 	{ 0x59, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, fully associative" },
685 	{ 0x5a, TLB_DATA0_2M_4M,	32,	" TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
686 	{ 0x5b, TLB_DATA_4K_4M,		64,	" TLB_DATA 4 KByte and 4 MByte pages" },
687 	{ 0x5c, TLB_DATA_4K_4M,		128,	" TLB_DATA 4 KByte and 4 MByte pages" },
688 	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
689 	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },
690 	{ 0x63, TLB_DATA_1G_2M_4M,	4,	" TLB_DATA 1 GByte pages, 4-way set associative"
691 						" (plus 32 entries TLB_DATA 2 MByte or 4 MByte pages, not encoded here)" },
692 	{ 0x6b, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 8-way associative" },
693 	{ 0x6c, TLB_DATA_2M_4M,		128,	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
695 	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
696 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
697 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
698 	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },
699 	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },
700 	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },
701 	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set associative" },
702 	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set associative" },
703 	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },
704 	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
705 	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },
706 	{ 0xc2, TLB_DATA_2M_4M,		16,	" TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
707 	{ 0xca, STLB_4K,		512,	" STLB 4 KByte pages, 4-way associative" },
807 	unsigned int regs[4];  in intel_detect_tlb()
810 	if (c->cpuid_level < 2)  in intel_detect_tlb()
820 		for (j = 0 ; j < 4 ; j++)  in intel_detect_tlb()
835 		{ .family = 4, .model_names =
837 			  [0] = "486 DX-25/33",
838 			  [1] = "486 DX-50",
841 			  [4] = "486 SL",
843 			  [7] = "486 DX/2-WB",
844 			  [8] = "486 DX/4",
845 			  [9] = "486 DX/4-WB"
850 			  [0] = "Pentium 60/66 A-step",
852 			  [2] = "Pentium 75 - 200",
854 			  [4] = "Pentium MMX",
855 			  [7] = "Mobile Pentium 75 - 200",
862 			  [0] = "Pentium Pro A-step",
865 			  [4] = "Pentium II (Deschutes)",
876 			  [0] = "Pentium 4 (Unknown)",
877 			  [1] = "Pentium 4 (Willamette)",
878 			  [2] = "Pentium 4 (Northwood)",
879 			  [4] = "Pentium 4 (Foster)",
880 			  [5] = "Pentium 4 (Foster)",
898  * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
912  * get_this_hybrid_cpu_native_id() - Get the native id of this hybrid CPU
923 	       (BIT_ULL(X86_HYBRID_CPU_TYPE_ID_SHIFT) - 1);  in get_this_hybrid_cpu_native_id()