14 #define ACE_PRESENT	(1 << 6)
15 #define ACE_ENABLED	(1 << 7)
16 #define ACE_FCR		(1 << 28)	/* MSR_VIA_FCR */
18 #define RNG_PRESENT	(1 << 2)
19 #define RNG_ENABLED	(1 << 3)
20 #define RNG_ENABLE	(1 << 6)	/* MSR_VIA_RNG */
22 static void init_c3(struct cpuinfo_x86 *c)  in init_c3()  argument
49 		c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);  in init_c3()
53 	if (c->x86_model >= 6 && c->x86_model <= 13) {  in init_c3()
55 		lo |= (1<<1 | 1<<7);  in init_c3()
57 		set_cpu_cap(c, X86_FEATURE_CX8);  in init_c3()
61 	if (c->x86_model >= 6 && c->x86_model < 9)  in init_c3()
62 		set_cpu_cap(c, X86_FEATURE_3DNOW);  in init_c3()
64 	if (c->x86 == 0x6 && c->x86_model >= 0xf) {  in init_c3()
65 		c->x86_cache_alignment = c->x86_clflush_size * 2;  in init_c3()
66 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);  in init_c3()
69 	if (c->x86 >= 7)  in init_c3()
70 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);  in init_c3()
74 		ECX8		= 1<<1,
75 		EIERRINT	= 1<<2,
76 		DPM		= 1<<3,
77 		DMCE		= 1<<4,
78 		DSTPCLK		= 1<<5,
79 		ELINEAR		= 1<<6,
80 		DSMC		= 1<<7,
81 		DTLOCK		= 1<<8,
82 		EDCTLB		= 1<<8,
83 		EMMX		= 1<<9,
84 		DPDC		= 1<<11,
85 		EBRPRED		= 1<<12,
86 		DIC		= 1<<13,
87 		DDC		= 1<<14,
88 		DNA		= 1<<15,
89 		ERETSTK		= 1<<16,
90 		E2MMX		= 1<<19,
91 		EAMD3D		= 1<<20,
94 static void early_init_centaur(struct cpuinfo_x86 *c)  in early_init_centaur()  argument
98 	if (c->x86 == 5)  in early_init_centaur()
99 		set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);  in early_init_centaur()
101 	if ((c->x86 == 6 && c->x86_model >= 0xf) ||  in early_init_centaur()
102 	    (c->x86 >= 7))  in early_init_centaur()
103 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);  in early_init_centaur()
106 	set_cpu_cap(c, X86_FEATURE_SYSENTER32);  in early_init_centaur()
108 	if (c->x86_power & (1 << 8)) {  in early_init_centaur()
109 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);  in early_init_centaur()
110 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);  in early_init_centaur()
114 static void init_centaur(struct cpuinfo_x86 *c)  in init_centaur()  argument
125 	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway  in init_centaur()
127 	clear_cpu_cap(c, 0*32+31);  in init_centaur()
129 	early_init_centaur(c);  in init_centaur()
130 	init_intel_cacheinfo(c);  in init_centaur()
132 	if (c->cpuid_level > 9) {  in init_centaur()
138 		 * Counters(eax[15:8]) should be greater than 1;  in init_centaur()
140 		if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))  in init_centaur()
141 			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);  in init_centaur()
145 	if (c->x86 == 5) {  in init_centaur()
146 		switch (c->x86_model) {  in init_centaur()
152 			clear_cpu_cap(c, X86_FEATURE_TSC);  in init_centaur()
155 			switch (c->x86_stepping) {  in init_centaur()
191 		set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);  in init_centaur()
193 		set_cpu_cap(c, X86_FEATURE_CX8);  in init_centaur()
195 		if (c->x86_model >= 8)  in init_centaur()
196 			set_cpu_cap(c, X86_FEATURE_3DNOW);  in init_centaur()
202 			c->x86_cache_size = (cc>>24)+(dd>>24);  in init_centaur()
204 		sprintf(c->x86_model_id, "WinChip %s", name);  in init_centaur()
207 	if (c->x86 == 6 || c->x86 >= 7)  in init_centaur()
208 		init_c3(c);  in init_centaur()
210 	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);  in init_centaur()
213 	init_ia32_feat_ctl(c);  in init_centaur()
218 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)  in centaur_size_cache()  argument
221 	if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))  in centaur_size_cache()
225 	 * There's also an erratum in Nehemiah stepping 1, which  in centaur_size_cache()
229 	if ((c->x86 == 6) && (c->x86_model == 9) &&  in centaur_size_cache()
230 				(c->x86_stepping == 1) && (size == 65))  in centaur_size_cache()
231 		size -= 1;  in centaur_size_cache()