Lines Matching +full:auto +full:- +full:switching
1 // SPDX-License-Identifier: GPL-2.0
6 * - Rafael R. Reilova (moved everything from head.S),
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
20 #include <asm/spec-ctrl.h>
24 #include <asm/processor-flags.h>
53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
89 * When KERNEL_IBRS this MSR is written on return-to-user, unless in update_spec_ctrl_cond()
210 hostval = ssbd_tif_to_spec_ctrl(ti->flags); in x86_virt_spec_ctrl()
239 /* Default mitigation for MDS-affected CPUs */
258 /* Default mitigation for TAA-affected CPUs */
312 return -EINVAL; in mds_cmdline()
402 return -EINVAL; in tsx_async_abort_parse_cmdline()
450 * mitigations, disable KVM-only mitigation in that case. in mmio_select_mitigation()
458 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can in mmio_select_mitigation()
490 return -EINVAL; in mmio_stale_data_parse_cmdline()
535 return -EINVAL; in rfds_parse_cmdline()
608 * As these mitigations are inter-related and rely on VERW instruction in md_clear_select_mitigation()
703 return -EINVAL; in srbds_parse_cmdline()
867 return -EINVAL; in gds_parse_cmdline()
910 * Consider SMAP to be non-functional as a mitigation on these in smap_works_speculatively()
929 * path of a conditional swapgs with a user-controlled GS in spectre_v1_select_mitigation()
954 * Enable lfences in the kernel entry (non-swapgs) in spectre_v1_select_mitigation()
1013 return -EINVAL; in retbleed_parse_cmdline()
1024 } else if (!strcmp(str, "auto")) { in retbleed_parse_cmdline()
1138 * software-based untraining so clear those in case some in retbleed_select_mitigation()
1214 return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; in spectre_v2_module_string()
1281 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
1291 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
1340 pr_err("Unknown user space protection option (%s). Switching to default\n", arg); in spectre_v2_parse_user_cmdline()
1402 "always-on" : "conditional"); in spectre_v2_user_select_mitigation()
1409 * Intel's Enhanced IBRS also protects against cross-thread branch target in spectre_v2_user_select_mitigation()
1410 * injection in user-mode as the IBRS bit remains always set which in spectre_v2_user_select_mitigation()
1411 * implicitly enables cross-thread protections. However, in legacy IBRS in spectre_v2_user_select_mitigation()
1414 * These modes therefore disable the implicit cross-thread protection, in spectre_v2_user_select_mitigation()
1425 * If STIBP support is not being forced, check if STIBP always-on in spectre_v2_user_select_mitigation()
1436 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n"); in spectre_v2_user_select_mitigation()
1470 { "auto", SPECTRE_V2_CMD_AUTO, false },
1503 pr_err("unknown option (%s). Switching to default mode\n", arg); in spectre_v2_parse_cmdline()
1513 pr_err("%s selected but not compiled in. Switching to AUTO select\n", in spectre_v2_parse_cmdline()
1522 pr_err("%s selected but CPU doesn't have Enhanced or Automatic IBRS. Switching to AUTO select\n", in spectre_v2_parse_cmdline()
1530 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n", in spectre_v2_parse_cmdline()
1536 pr_err("%s selected but not compiled in. Switching to AUTO select\n", in spectre_v2_parse_cmdline()
1542 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n", in spectre_v2_parse_cmdline()
1548 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n", in spectre_v2_parse_cmdline()
1554 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n", in spectre_v2_parse_cmdline()
1576 /* Disable in-kernel use of non-RSB RET predictors */
1611 * user-space-poisoned RSB entries. in spectre_v2_determine_rsb_fill_type_at_vmexit()
1625 pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n"); in spectre_v2_determine_rsb_fill_type_at_vmexit()
1670 return -EINVAL; in spectre_bhi_parse_cmdline()
1722 * If the CPU is not affected and the command line mode is NONE or AUTO in spectre_v2_select_mitigation()
1819 * JMPs gets protection against BHI and Intramode-BTI, but RET in spectre_v2_select_mitigation()
1820 * prediction from a non-RSB predictor is still a risk. in spectre_v2_select_mitigation()
1842 * which could have a user-poisoned BTB or BHB entry. in spectre_v2_select_mitigation()
1847 * When IBRS or eIBRS is enabled, the "user -> kernel" attack in spectre_v2_select_mitigation()
1852 * The "user -> user" attack scenario is mitigated by RSB filling. in spectre_v2_select_mitigation()
1856 * If the 'next' in-kernel return stack is shorter than 'prev', in spectre_v2_select_mitigation()
1857 * 'next' could be tricked into speculating with a user-poisoned RSB in spectre_v2_select_mitigation()
1860 * The "user -> kernel" attack scenario is mitigated by SMEP and in spectre_v2_select_mitigation()
1863 * The "user -> user" scenario, also known as SpectreBHB, requires in spectre_v2_select_mitigation()
1869 * FIXME: Is this pointless for retbleed-affected AMD? in spectre_v2_select_mitigation()
1884 * the CPU supports Enhanced IBRS, kernel might un-intentionally not in spectre_v2_select_mitigation()
1924 mask & SPEC_CTRL_STIBP ? "always-on" : "off"); in update_stibp_strict()
1963 …n, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for…
1964 …n, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_ab…
1965 …n, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mm…
2051 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
2084 pr_err("unknown option (%s). Switching to default mode\n", arg); in ssb_parse_cmdline()
2130 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. in __ssb_select_mitigation()
2131 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass in __ssb_select_mitigation()
2132 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation in __ssb_select_mitigation()
2170 * task, but for a non-current task delay setting the CPU in task_update_spec_tif()
2184 return -EPERM; in l1d_flush_prctl_set()
2188 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); in l1d_flush_prctl_set()
2191 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH); in l1d_flush_prctl_set()
2194 return -ERANGE; in l1d_flush_prctl_set()
2202 return -ENXIO; in ssb_prctl_set()
2208 return -EPERM; in ssb_prctl_set()
2226 return -EPERM; in ssb_prctl_set()
2232 return -ERANGE; in ssb_prctl_set()
2261 * updated, unless it was force-disabled by a previous prctl in ib_prctl_set()
2270 return -EPERM; in ib_prctl_set()
2283 return -EPERM; in ib_prctl_set()
2296 return -ERANGE; in ib_prctl_set()
2312 return -ENODEV; in arch_prctl_spec_ctrl_set()
2332 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH)) in l1d_flush_prctl_get()
2392 return -ENODEV; in arch_prctl_spec_ctrl_get()
2411 /* Default mitigation for L1TF-affected CPUs */
2436 if (c->x86 != 6) in override_cache_bits()
2439 switch (c->x86_vfm) { in override_cache_bits()
2453 if (c->x86_cache_bits < 44) in override_cache_bits()
2454 c->x86_cache_bits = 44; in override_cache_bits()
2494 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { in l1tf_select_mitigation()
2499 …pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help y… in l1tf_select_mitigation()
2512 return -EINVAL; in l1tf_cmdline()
2570 return -EINVAL; in srso_parse_cmdline()
2576 else if (!strcmp(str, "safe-ret")) in srso_parse_cmdline()
2580 else if (!strcmp(str, "ibpb-vmexit")) in srso_parse_cmdline()
2589 #define SRSO_NOTICE "WARNING: See https://kernel.org/doc/html/latest/admin-guide/hw-vuln/srso.html …
2620 pr_warn("IBPB-extending microcode not applied!\n"); in srso_select_mitigation()
2672 * software-based untraining so clear those in case some in srso_select_mitigation()
2739 [VMENTER_L1D_FLUSH_AUTO] = "auto",
2854 return "; STIBP: always-on"; in stibp_state()
2867 return "; IBPB: always-on"; in ibpb_state()
2880 return "; PBRSB-eIBRS: SW sequence"; in pbrsb_eibrs_state()
2882 return "; PBRSB-eIBRS: Vulnerable"; in pbrsb_eibrs_state()
2884 return "; PBRSB-eIBRS: Not affected"; in pbrsb_eibrs_state()
2941 return sysfs_emit(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n"); in retbleed_show_state()