Lines Matching +full:non +full:- +full:secure
1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Secure AVIC Support (SEV-SNP Guests)
12 #include <linux/percpu-defs.h>
33 return &per_cpu_ptr(savic_page, cpu)->regs[offset]; in get_reg_bitmap()
50 * When Secure AVIC is enabled, RDMSR/WRMSR of the APIC registers
51 * result in #VC exception (for non-accelerated register accesses)
113 IS_ALIGNED(reg - 4, 16)), in savic_read()
118 pr_err("Error reading unknown Secure AVIC reg offset 0x%x\n", reg); in savic_read()
126 * On WRMSR to APIC_SELF_IPI register by the guest, Secure AVIC hardware
129 * the vCPU. So, self IPIs are hardware-accelerated.
234 if (IS_ALIGNED(reg - 4, 16)) { in savic_write()
240 pr_err("Error writing unknown Secure AVIC reg offset 0x%x\n", reg); in savic_write()
311 if (WARN_ONCE(vec == -1, "EOI write while no active interrupt in APIC_ISR")) in savic_eoi()
314 /* Is level-triggered interrupt? */ in savic_eoi()
318 * Propagate the EOI write to the hypervisor for level-triggered in savic_eoi()
320 * care of re-evaluating interrupt state. in savic_eoi()
325 * Hardware clears APIC_ISR and re-evaluates the interrupt state in savic_eoi()
335 /* Disable Secure AVIC */ in savic_teardown()
347 * Before Secure AVIC is enabled, APIC MSR reads are intercepted. in savic_setup()
356 * present when the vCPU is running in order for Secure AVIC to in savic_setup()
378 pr_err("Secure AVIC enabled in non x2APIC mode\n"); in savic_probe()
392 .name = "secure avic x2apic",