Lines Matching +full:delta +full:- +full:x +full:- +full:threshold
1 // SPDX-License-Identifier: GPL-2.0-only
13 * Mikael Pettersson : Power Management for UP-APIC.
44 #include <asm/pc-conf-reg.h>
66 #include <asm/intel-family.h>
125 * +1=force-enable
215 * so apic->write/read doesn't do anything
243 * lapic_get_maxlvt - get the maximum number of local vector table entries
248 * - we always have APIC integrated on 64bit mode in lapic_get_maxlvt()
249 * - 82489DXs do not report # of LVT entries in lapic_get_maxlvt()
301 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, in __setup_APIC_LVTT()
326 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
367 pr_info("LVT offset %d assigned for vector 0x%02x\n", in reserve_eilvt_offset()
390 "vector 0x%x, but the register is already in use for " in setup_APIC_eilvt()
391 "vector 0x%x on another cpu\n", in setup_APIC_eilvt()
393 return -EINVAL; in setup_APIC_eilvt()
398 "vector 0x%x, but the register is already in use for " in setup_APIC_eilvt()
399 "vector 0x%x on this cpu\n", in setup_APIC_eilvt()
401 return -EBUSY; in setup_APIC_eilvt()
413 static int lapic_next_event(unsigned long delta, in lapic_next_event() argument
416 apic_write(APIC_TMICT, delta); in lapic_next_event()
420 static int lapic_next_deadline(unsigned long delta, in lapic_next_deadline() argument
429 wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); in lapic_next_deadline()
438 if (evt->features & CLOCK_EVT_FEAT_DUMMY) in lapic_timer_shutdown()
464 if (evt->features & CLOCK_EVT_FEAT_DUMMY) in lapic_timer_set_periodic_oneshot()
508 .irq = -1,
557 rev = (u32)m->driver_data; in apic_validate_deadline_timer()
564 "please update microcode to version: 0x%x (or later)\n", rev); in apic_validate_deadline_timer()
583 levt->cpumask = cpumask_of(smp_processor_id()); in setup_APIC_timer()
586 levt->name = "lapic-deadline"; in setup_APIC_timer()
587 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | in setup_APIC_timer()
589 levt->set_next_event = lapic_next_deadline; in setup_APIC_timer()
616 * The clockevent device's ->mult and ->shift can both be in lapic_update_tsc_freq()
646 static __initdata int lapic_cal_loops = -1;
684 calibrate_by_pmtimer(u32 deltapm, long *delta, long *deltatsc) in calibrate_by_pmtimer() argument
692 return -1; in calibrate_by_pmtimer()
695 apic_pr_verbose("... PM-Timer delta = %u\n", deltapm); in calibrate_by_pmtimer()
699 return -1; in calibrate_by_pmtimer()
703 if (deltapm > (pm_100ms - pm_thresh) && in calibrate_by_pmtimer()
705 apic_pr_verbose("... PM-Timer result ok\n"); in calibrate_by_pmtimer()
711 pr_warn("APIC calibration not consistent with PM-Timer: %ldms instead of 100ms\n", in calibrate_by_pmtimer()
715 res = (((u64)(*delta)) * pm_100ms); in calibrate_by_pmtimer()
717 pr_info("APIC delta adjusted to PM-Timer: " in calibrate_by_pmtimer()
718 "%lu (%ld)\n", (unsigned long)res, *delta); in calibrate_by_pmtimer()
719 *delta = (long)res; in calibrate_by_pmtimer()
725 apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n", in calibrate_by_pmtimer()
736 return -1; in lapic_init_clockevent()
797 long delta, deltatsc; in calibrate_APIC_clock() local
856 if ((tsc_now - tsc_start) >= tsc_perj) { in calibrate_APIC_clock()
879 /* Build delta t1-t2 as apic timer counts down */ in calibrate_APIC_clock()
880 delta = lapic_cal_t1 - lapic_cal_t2; in calibrate_APIC_clock()
881 apic_pr_verbose("... lapic delta = %ld\n", delta); in calibrate_APIC_clock()
883 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); in calibrate_APIC_clock()
886 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, in calibrate_APIC_clock()
887 &delta, &deltatsc); in calibrate_APIC_clock()
889 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; in calibrate_APIC_clock()
892 apic_pr_verbose("..... delta %ld\n", delta); in calibrate_APIC_clock()
912 return -1; in calibrate_APIC_clock()
915 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; in calibrate_APIC_clock()
928 levt->event_handler = lapic_cal_handler; in calibrate_APIC_clock()
930 lapic_cal_loops = -1; in calibrate_APIC_clock()
942 /* Jiffies delta */ in calibrate_APIC_clock()
943 deltaj = lapic_cal_j2 - lapic_cal_j1; in calibrate_APIC_clock()
944 apic_pr_verbose("... jiffies delta = %lu\n", deltaj); in calibrate_APIC_clock()
947 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) in calibrate_APIC_clock()
950 levt->features |= CLOCK_EVT_FEAT_DUMMY; in calibrate_APIC_clock()
954 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { in calibrate_APIC_clock()
956 return -1; in calibrate_APIC_clock()
1024 * its possible that when we get here evt->event_handler is NULL. in local_apic_timer_interrupt()
1028 if (!evt->event_handler) { in local_apic_timer_interrupt()
1037 * the NMI deadlock-detector uses this. in local_apic_timer_interrupt()
1041 evt->event_handler(evt); in local_apic_timer_interrupt()
1049 * [ if a single-CPU system runs an SMP kernel then we call the local
1069 * clear_local_APIC - shutdown the local APIC
1089 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ in clear_local_APIC()
1094 * any level-triggered sources. in clear_local_APIC()
1143 * apic_soft_disable - Clears and software disables the local APIC on hotplug
1166 * disable_local_APIC - clear and disable the local APIC
1173 if (apic->teardown) in disable_local_APIC()
1174 apic->teardown(); in disable_local_APIC()
1195 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1196 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1220 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1225 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not in sync_Arb_IDs()
1252 /* On 64-bit, the APIC must be integrated, Check local APIC only */ in __apic_intr_mode_select()
1259 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ in __apic_intr_mode_select()
1312 * through-I/O-APIC virtual wire mode might be active. in init_bsp_APIC()
1395 if (apic->disable_esr) { in lapic_setup_esr()
1399 * ESR disabled - we can't do anything useful with the in lapic_setup_esr()
1400 * errors anyway - mbligh in lapic_setup_esr()
1422 apic_pr_verbose("ESR value before enabling vector: 0x%08x after: 0x%08x\n", in lapic_setup_esr()
1442 isr->regs[i] = apic_read(APIC_ISR + i * 0x10); in apic_check_and_eoi_isr()
1445 if (bitmap_empty(isr->map, APIC_IR_BITS)) in apic_check_and_eoi_isr()
1455 for_each_set_bit(bit, isr->map, APIC_IR_BITS) in apic_check_and_eoi_isr()
1460 isr->regs[i] = apic_read(APIC_ISR + i * 0x10); in apic_check_and_eoi_isr()
1462 return bitmap_empty(isr->map, APIC_IR_BITS); in apic_check_and_eoi_isr()
1494 * setup_local_APIC - setup the local APIC
1509 if (apic->setup) in setup_local_APIC()
1510 apic->setup(); in setup_local_APIC()
1521 /* Pound the ESR really hard over the head with a big hammer - mbligh */ in setup_local_APIC()
1522 if (lapic_is_integrated() && apic->disable_esr) { in setup_local_APIC()
1531 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel in setup_local_APIC()
1536 if (apic->init_apic_ldr) in setup_local_APIC()
1537 apic->init_apic_ldr(); in setup_local_APIC()
1540 * Set Task Priority to 'accept all except vectors 0-31'. An APIC in setup_local_APIC()
1541 * vector in the 16-31 range could be delivered if TPR == 0, but we in setup_local_APIC()
1570 * away, oh well :-( in setup_local_APIC()
1572 * [ This bug can be reproduced easily with a level-triggered in setup_local_APIC()
1579 * like LRU than MRU (the short-term load is more even across CPUs). in setup_local_APIC()
1583 * - enable focus processor (bit==0) in setup_local_APIC()
1584 * - 64bit mode always use processor focus in setup_local_APIC()
1601 * set up through-local-APIC on the boot CPU's LINT0. This is not in setup_local_APIC()
1602 * strictly necessary in pure symmetric-IO mode, but sometimes in setup_local_APIC()
1606 * TODO: set up through-local-APIC from through-I/O-APIC? --macro in setup_local_APIC()
1742 pr_warn("Apicid: %08x, cannot enforce nox2apic\n", in setup_nox2apic()
1793 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); in x2apic_disable()
1796 pr_warn("Cannot disable locked x2apic, id: %08x\n", x2apic_id); in x2apic_disable()
1844 * used for non-remapped IRQ domains. in try_to_enable_x2apic()
1901 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); in enable_IR_x2apic()
1911 pr_info("Saving IO-APIC state failed: %d\n", ret); in enable_IR_x2apic()
1916 legacy_pic->mask_all(); in enable_IR_x2apic()
1927 legacy_pic->restore_mask(); in enable_IR_x2apic()
1933 * Detect and enable local APICs on non-SMP boards.
1935 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1992 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); in apic_force_enable()
2030 * Over-ride BIOS and try to enable the local APIC only if in detect_init_APIC()
2034 pr_info("Local APIC disabled by BIOS -- " in detect_init_APIC()
2056 * init_apic_mappings - initialize APIC mappings
2125 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", in handle_spurious_interrupt()
2129 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", in handle_spurious_interrupt()
2137 * spurious_interrupt - Catch all for interrupts raised on unused vectors
2174 /* First tickle the hardware, only then report what went on. -- REW */ in DEFINE_IDTENTRY_SYSVEC()
2181 apic_pr_debug("APIC error on CPU%d: %02x", smp_processor_id(), v); in DEFINE_IDTENTRY_SYSVEC()
2197 * connect_bsp_APIC - attach the APIC to the interrupt system
2218 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2286 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; in __irq_msi_compose_msg()
2287 msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical; in __irq_msi_compose_msg()
2288 msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF; in __irq_msi_compose_msg()
2290 msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED; in __irq_msi_compose_msg()
2291 msg->arch_data.vector = cfg->vector; in __irq_msi_compose_msg()
2293 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; in __irq_msi_compose_msg()
2298 * address APICs which can't be addressed in the normal 32-bit in __irq_msi_compose_msg()
2301 * 5-11 to be used, giving support for 15 bits of APIC IDs in total. in __irq_msi_compose_msg()
2304 msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8; in __irq_msi_compose_msg()
2305 else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000) in __irq_msi_compose_msg()
2306 msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8; in __irq_msi_compose_msg()
2308 WARN_ON_ONCE(cfg->dest_apicid > 0xFF); in __irq_msi_compose_msg()
2313 u32 dest = msg->arch_addr_lo.destid_0_7; in x86_msi_msg_get_destid()
2316 dest |= msg->arch_addr_hi.destid_8_31 << 8; in x86_msi_msg_get_destid()
2327 * apic_bsp_setup - Setup function for local apic and io-apic
2444 * IO-APIC and PIC have their own resume routines. in lapic_resume()
2447 * and interrupt-remapping. in lapic_resume()
2450 legacy_pic->mask_all(); in lapic_resume()
2503 * This device has no shutdown method - fully functioning local APICs
2544 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); in set_multi()
2571 * apic_is_clustered_box() -- Check if we can expect good TSC
2575 * multi-chassis.
2621 return -EINVAL; in apic_set_verbosity()
2635 return -EINVAL; in apic_set_verbosity()
2646 return -1; in lapic_insert_resource()
2650 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; in lapic_insert_resource()
2665 return -EINVAL; in apic_set_extnmi()
2675 return -EINVAL; in apic_set_extnmi()