26  *   before entering C3.
42 		 * Today all MP CPUs that support C3 share cache.  in acpi_processor_power_init_bm_check()
44 		 * entering C3 type state.  in acpi_processor_power_init_bm_check()
52 	 * is not required while entering C3 type state.  in acpi_processor_power_init_bm_check()
63 			 * core can keep cache coherence with each other while entering C3  in acpi_processor_power_init_bm_check()
66 			 * entering C3 type state.  in acpi_processor_power_init_bm_check()
72 			 * not required while entering C3 type state.  in acpi_processor_power_init_bm_check()
80 		 * All Zhaoxin CPUs that support C3 share cache.  in acpi_processor_power_init_bm_check()
82 		 * entering C3 type state.  in acpi_processor_power_init_bm_check()
88 		 * is not required while entering C3 type state.  in acpi_processor_power_init_bm_check()
94 		 * For all AMD Zen or newer CPUs that support C3, caches  in acpi_processor_power_init_bm_check()
95 		 * should not be flushed by software while entering C3  in acpi_processor_power_init_bm_check()
103 		 * required while entering C3 type state.  in acpi_processor_power_init_bm_check()
150 	/* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */  in acpi_processor_ffh_cstate_probe_cpu()