Lines Matching +full:0 +full:x00000802
23 #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
51 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
95 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
97 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
98 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
99 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
100 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
101 #define VM_EXIT_SAVE_IA32_PAT 0x00040000
102 #define VM_EXIT_LOAD_IA32_PAT 0x00080000
103 #define VM_EXIT_SAVE_IA32_EFER 0x00100000
104 #define VM_EXIT_LOAD_IA32_EFER 0x00200000
105 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
106 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000
107 #define VM_EXIT_PT_CONCEAL_PIP 0x01000000
108 #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
110 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
112 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
113 #define VM_ENTRY_IA32E_MODE 0x00000200
114 #define VM_ENTRY_SMM 0x00000400
115 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
116 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
117 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
118 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
119 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000
120 #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
121 #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
123 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
126 #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28)
138 return vmx_basic & GENMASK_ULL(30, 0); in vmx_basic_vmcs_revision_id()
169 return vmx_misc & GENMASK_ULL(4, 0); in vmx_misc_preemption_timer_rate()
189 VIRTUAL_PROCESSOR_ID = 0x00000000,
190 POSTED_INTR_NV = 0x00000002,
191 LAST_PID_POINTER_INDEX = 0x00000008,
192 GUEST_ES_SELECTOR = 0x00000800,
193 GUEST_CS_SELECTOR = 0x00000802,
194 GUEST_SS_SELECTOR = 0x00000804,
195 GUEST_DS_SELECTOR = 0x00000806,
196 GUEST_FS_SELECTOR = 0x00000808,
197 GUEST_GS_SELECTOR = 0x0000080a,
198 GUEST_LDTR_SELECTOR = 0x0000080c,
199 GUEST_TR_SELECTOR = 0x0000080e,
200 GUEST_INTR_STATUS = 0x00000810,
201 GUEST_PML_INDEX = 0x00000812,
202 HOST_ES_SELECTOR = 0x00000c00,
203 HOST_CS_SELECTOR = 0x00000c02,
204 HOST_SS_SELECTOR = 0x00000c04,
205 HOST_DS_SELECTOR = 0x00000c06,
206 HOST_FS_SELECTOR = 0x00000c08,
207 HOST_GS_SELECTOR = 0x00000c0a,
208 HOST_TR_SELECTOR = 0x00000c0c,
209 IO_BITMAP_A = 0x00002000,
210 IO_BITMAP_A_HIGH = 0x00002001,
211 IO_BITMAP_B = 0x00002002,
212 IO_BITMAP_B_HIGH = 0x00002003,
213 MSR_BITMAP = 0x00002004,
214 MSR_BITMAP_HIGH = 0x00002005,
215 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
216 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
217 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
218 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
219 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
220 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
221 PML_ADDRESS = 0x0000200e,
222 PML_ADDRESS_HIGH = 0x0000200f,
223 TSC_OFFSET = 0x00002010,
224 TSC_OFFSET_HIGH = 0x00002011,
225 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
226 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
227 APIC_ACCESS_ADDR = 0x00002014,
228 APIC_ACCESS_ADDR_HIGH = 0x00002015,
229 POSTED_INTR_DESC_ADDR = 0x00002016,
230 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
231 VM_FUNCTION_CONTROL = 0x00002018,
232 VM_FUNCTION_CONTROL_HIGH = 0x00002019,
233 EPT_POINTER = 0x0000201a,
234 EPT_POINTER_HIGH = 0x0000201b,
235 EOI_EXIT_BITMAP0 = 0x0000201c,
236 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
237 EOI_EXIT_BITMAP1 = 0x0000201e,
238 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
239 EOI_EXIT_BITMAP2 = 0x00002020,
240 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
241 EOI_EXIT_BITMAP3 = 0x00002022,
242 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
243 EPTP_LIST_ADDRESS = 0x00002024,
244 EPTP_LIST_ADDRESS_HIGH = 0x00002025,
245 VMREAD_BITMAP = 0x00002026,
246 VMREAD_BITMAP_HIGH = 0x00002027,
247 VMWRITE_BITMAP = 0x00002028,
248 VMWRITE_BITMAP_HIGH = 0x00002029,
249 VE_INFORMATION_ADDRESS = 0x0000202A,
250 VE_INFORMATION_ADDRESS_HIGH = 0x0000202B,
251 XSS_EXIT_BITMAP = 0x0000202C,
252 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
253 ENCLS_EXITING_BITMAP = 0x0000202E,
254 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F,
255 TSC_MULTIPLIER = 0x00002032,
256 TSC_MULTIPLIER_HIGH = 0x00002033,
257 TERTIARY_VM_EXEC_CONTROL = 0x00002034,
258 TERTIARY_VM_EXEC_CONTROL_HIGH = 0x00002035,
259 SHARED_EPT_POINTER = 0x0000203C,
260 PID_POINTER_TABLE = 0x00002042,
261 PID_POINTER_TABLE_HIGH = 0x00002043,
262 GUEST_PHYSICAL_ADDRESS = 0x00002400,
263 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
264 VMCS_LINK_POINTER = 0x00002800,
265 VMCS_LINK_POINTER_HIGH = 0x00002801,
266 GUEST_IA32_DEBUGCTL = 0x00002802,
267 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
268 GUEST_IA32_PAT = 0x00002804,
269 GUEST_IA32_PAT_HIGH = 0x00002805,
270 GUEST_IA32_EFER = 0x00002806,
271 GUEST_IA32_EFER_HIGH = 0x00002807,
272 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
273 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
274 GUEST_PDPTR0 = 0x0000280a,
275 GUEST_PDPTR0_HIGH = 0x0000280b,
276 GUEST_PDPTR1 = 0x0000280c,
277 GUEST_PDPTR1_HIGH = 0x0000280d,
278 GUEST_PDPTR2 = 0x0000280e,
279 GUEST_PDPTR2_HIGH = 0x0000280f,
280 GUEST_PDPTR3 = 0x00002810,
281 GUEST_PDPTR3_HIGH = 0x00002811,
282 GUEST_BNDCFGS = 0x00002812,
283 GUEST_BNDCFGS_HIGH = 0x00002813,
284 GUEST_IA32_RTIT_CTL = 0x00002814,
285 GUEST_IA32_RTIT_CTL_HIGH = 0x00002815,
286 HOST_IA32_PAT = 0x00002c00,
287 HOST_IA32_PAT_HIGH = 0x00002c01,
288 HOST_IA32_EFER = 0x00002c02,
289 HOST_IA32_EFER_HIGH = 0x00002c03,
290 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
291 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
292 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
293 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
294 EXCEPTION_BITMAP = 0x00004004,
295 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
296 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
297 CR3_TARGET_COUNT = 0x0000400a,
298 VM_EXIT_CONTROLS = 0x0000400c,
299 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
300 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
301 VM_ENTRY_CONTROLS = 0x00004012,
302 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
303 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
304 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
305 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
306 TPR_THRESHOLD = 0x0000401c,
307 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
308 PLE_GAP = 0x00004020,
309 PLE_WINDOW = 0x00004022,
310 NOTIFY_WINDOW = 0x00004024,
311 VM_INSTRUCTION_ERROR = 0x00004400,
312 VM_EXIT_REASON = 0x00004402,
313 VM_EXIT_INTR_INFO = 0x00004404,
314 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
315 IDT_VECTORING_INFO_FIELD = 0x00004408,
316 IDT_VECTORING_ERROR_CODE = 0x0000440a,
317 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
318 VMX_INSTRUCTION_INFO = 0x0000440e,
319 GUEST_ES_LIMIT = 0x00004800,
320 GUEST_CS_LIMIT = 0x00004802,
321 GUEST_SS_LIMIT = 0x00004804,
322 GUEST_DS_LIMIT = 0x00004806,
323 GUEST_FS_LIMIT = 0x00004808,
324 GUEST_GS_LIMIT = 0x0000480a,
325 GUEST_LDTR_LIMIT = 0x0000480c,
326 GUEST_TR_LIMIT = 0x0000480e,
327 GUEST_GDTR_LIMIT = 0x00004810,
328 GUEST_IDTR_LIMIT = 0x00004812,
329 GUEST_ES_AR_BYTES = 0x00004814,
330 GUEST_CS_AR_BYTES = 0x00004816,
331 GUEST_SS_AR_BYTES = 0x00004818,
332 GUEST_DS_AR_BYTES = 0x0000481a,
333 GUEST_FS_AR_BYTES = 0x0000481c,
334 GUEST_GS_AR_BYTES = 0x0000481e,
335 GUEST_LDTR_AR_BYTES = 0x00004820,
336 GUEST_TR_AR_BYTES = 0x00004822,
337 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
338 GUEST_ACTIVITY_STATE = 0x00004826,
339 GUEST_SYSENTER_CS = 0x0000482A,
340 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
341 HOST_IA32_SYSENTER_CS = 0x00004c00,
342 CR0_GUEST_HOST_MASK = 0x00006000,
343 CR4_GUEST_HOST_MASK = 0x00006002,
344 CR0_READ_SHADOW = 0x00006004,
345 CR4_READ_SHADOW = 0x00006006,
346 CR3_TARGET_VALUE0 = 0x00006008,
347 CR3_TARGET_VALUE1 = 0x0000600a,
348 CR3_TARGET_VALUE2 = 0x0000600c,
349 CR3_TARGET_VALUE3 = 0x0000600e,
350 EXIT_QUALIFICATION = 0x00006400,
351 GUEST_LINEAR_ADDRESS = 0x0000640a,
352 GUEST_CR0 = 0x00006800,
353 GUEST_CR3 = 0x00006802,
354 GUEST_CR4 = 0x00006804,
355 GUEST_ES_BASE = 0x00006806,
356 GUEST_CS_BASE = 0x00006808,
357 GUEST_SS_BASE = 0x0000680a,
358 GUEST_DS_BASE = 0x0000680c,
359 GUEST_FS_BASE = 0x0000680e,
360 GUEST_GS_BASE = 0x00006810,
361 GUEST_LDTR_BASE = 0x00006812,
362 GUEST_TR_BASE = 0x00006814,
363 GUEST_GDTR_BASE = 0x00006816,
364 GUEST_IDTR_BASE = 0x00006818,
365 GUEST_DR7 = 0x0000681a,
366 GUEST_RSP = 0x0000681c,
367 GUEST_RIP = 0x0000681e,
368 GUEST_RFLAGS = 0x00006820,
369 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
370 GUEST_SYSENTER_ESP = 0x00006824,
371 GUEST_SYSENTER_EIP = 0x00006826,
372 HOST_CR0 = 0x00006c00,
373 HOST_CR3 = 0x00006c02,
374 HOST_CR4 = 0x00006c04,
375 HOST_FS_BASE = 0x00006c06,
376 HOST_GS_BASE = 0x00006c08,
377 HOST_TR_BASE = 0x00006c0a,
378 HOST_GDTR_BASE = 0x00006c0c,
379 HOST_IDTR_BASE = 0x00006c0e,
380 HOST_IA32_SYSENTER_ESP = 0x00006c10,
381 HOST_IA32_SYSENTER_EIP = 0x00006c12,
382 HOST_RSP = 0x00006c14,
383 HOST_RIP = 0x00006c16,
389 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
390 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
391 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
392 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
393 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
394 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
411 #define GUEST_INTR_STATE_STI 0x00000001
412 #define GUEST_INTR_STATE_MOV_SS 0x00000002
413 #define GUEST_INTR_STATE_SMI 0x00000004
414 #define GUEST_INTR_STATE_NMI 0x00000008
415 #define GUEST_INTR_STATE_ENCLAVE_INTR 0x00000010
418 #define GUEST_ACTIVITY_ACTIVE 0
426 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
427 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
428 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
430 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
431 #define REG_EAX (0 << 8)
451 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
452 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
453 #define TYPE_MOV_TO_DR (0 << 4)
455 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
461 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
462 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
463 #define TYPE_LINEAR_APIC_INST_READ (0 << 12)
477 #define VMX_AR_TYPE_MASK 0x0f
492 #define VMX_AR_RESERVD_MASK 0xfffe0f00
494 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
499 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
520 #define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */
527 #define VMX_EPTP_PWL_MASK 0x38ull
528 #define VMX_EPTP_PWL_4 0x18ull
529 #define VMX_EPTP_PWL_5 0x20ull
531 /* The EPTP memtype is encoded in bits 2:0, i.e. doesn't need to be shifted. */
532 #define VMX_EPTP_MT_MASK 0x7ull
535 #define VMX_EPT_READABLE_MASK 0x1ull
536 #define VMX_EPT_WRITABLE_MASK 0x2ull
537 #define VMX_EPT_EXECUTABLE_MASK 0x4ull
563 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
575 ENTRY_FAIL_DEFAULT = 0,
584 #define EPT_VIOLATION_ACC_READ BIT(0)
605 #define NOTIFY_VM_CONTEXT_INVALID BIT(0)