Lines Matching +full:11 +full:be
77 * be unpacked and written to a proper addresses
106 * If an event has alias it should be marked
137 * caller bits, otherwise the mapping won't be complete.
240 * This are the events which should be used in "Event Select"
242 * the kernel to determinate which CCCR and COUNTER should be
334 * MSR_P4_DAC_ESCR1: 10, 11
340 * MSR_P4_SAAT_ESCR1: 10, 11
346 * MSR_P4_SAAT_ESCR1: 10, 11
352 * MSR_P4_SAAT_ESCR1: 10, 11
404 * MSR_P4_FIRM_ESCR1: 10, 11
410 * MSR_P4_FIRM_ESCR1: 10, 11
416 * MSR_P4_FIRM_ESCR1: 10, 11
422 * MSR_P4_FIRM_ESCR1: 10, 11
428 * MSR_P4_FIRM_ESCR1: 10, 11
434 * MSR_P4_FIRM_ESCR1: 10, 11
440 * MSR_P4_FIRM_ESCR1: 10, 11
446 * MSR_P4_FIRM_ESCR1: 10, 11
494 * MSR_P4_DAC_ESCR1: 10, 11
644 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11),
656 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
678 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11),
692 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
836 * be found in Intel SDM but it should be noted that
842 * and should be either 0 or set to some predefined
848 * 7-11: reserved