1 /* SPDX-License-Identifier: GPL-2.0 */
16  * perf-MSRs are not shared and every thread has its
17  * own perf-MSRs set)
21 #define ARCH_P4_MAX_ESCR	(ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
25 #define ARCH_P4_CNTRVAL_MASK	((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
26 #define ARCH_P4_UNFLAGGED_BIT	((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
40 #define P4_ESCR_EVENT(v)	((v) << P4_ESCR_EVENT_SHIFT)  argument
41 #define P4_ESCR_EMASK(v)	((v) << P4_ESCR_EVENTMASK_SHIFT)  argument
42 #define P4_ESCR_TAG(v)		((v) << P4_ESCR_TAG_SHIFT)  argument
62 #define P4_CCCR_THRESHOLD(v)		((v) << P4_CCCR_THRESHOLD_SHIFT)  argument
63 #define P4_CCCR_ESEL(v)			((v) << P4_CCCR_ESCR_SELECT_SHIFT)  argument
81 #define p4_config_pack_escr(v)		(((u64)(v)) << 32)  argument
82 #define p4_config_pack_cccr(v)		(((u64)(v)) & 0xffffffffULL)  argument
83 #define p4_config_unpack_escr(v)	(((u64)(v)) >> 32)  argument
84 #define p4_config_unpack_cccr(v)	(((u64)(v)) & 0xffffffffULL)  argument
86 #define p4_config_unpack_emask(v)			\  argument
88 		u32 t = p4_config_unpack_escr((v));	\
94 #define p4_config_unpack_event(v)			\  argument
96 		u32 t = p4_config_unpack_escr((v));	\
207 	 * non-HT machines (on HT machines we count TS events  in p4_default_cccr_conf()
304  * processor builds (family 0FH, models 01H-02H). These MSRs
487 	 * MSR_P4_ALF_ESCR0:	12, 13, 16
523 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
529 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
535 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
541 	 * MSR_P4_CRU_ESCR0:	12, 13, 16
547 	 * MSR_P4_CRU_ESCR0:	12, 13, 16
553 	 * MSR_P4_RAT_ESCR0:	12, 13, 16
559 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
565 	 * MSR_P4_CRU_ESCR0:	12, 13, 16
571 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
577 	 * MSR_P4_CRU_ESCR2:	12, 13, 16
583 	 * MSR_P4_CRU_ESCR0:	12, 13, 16
679 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12),
693 	P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
800 #define p4_config_unpack_metric(v)	(((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)  argument
801 #define p4_config_unpack_pebs(v)	(((u64)(v)) & P4_PEBS_CONFIG_MASK)  argument
803 #define p4_config_pebs_has(v, mask)	(p4_config_unpack_pebs(v) & (mask))  argument
846  *    -----------
847  *      0-6: P4_PEBS_METRIC enum
848  *     7-11:                    reserved
849  *       12:                    reserved (Enable)
850  *    13-15:                    reserved (ESCR select)
851  *    16-17: Active Thread
854  *    20-23: Threshold
859  *    28-29:                    reserved
864  *    ------------
870  *      5-8: Tag Value
871  *     9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
872  *    25-30: enum P4_EVENTS