1 /* SPDX-License-Identifier: GPL-2.0 */
155 /* Steal the highest bit of pebs_data_cfg for SW usage */
169 	unsigned int full;  member
182 	unsigned int full;  member
193 	unsigned int full;  member
207 		/* Counters Sub-Leaf */
209 		/* Auto Counter Reload Sub-Leaf */
211 		/* Events Sub-Leaf */
215 	unsigned int            full;  member
222 		/* EQ-bit Supported */
226 	unsigned int            full;  member
237 		/* Deep C-state Reset */
242 	unsigned int		full;  member
251 		/* Call-stack Mode Supported */
254 	unsigned int            full;  member
259 		/* Mispredict Bit Supported */
269 	unsigned int            full;  member
287 	unsigned int		full;  member
302  * Fixed-purpose performance events:
310  * All the fixed-mode PMCs are configured via this single MSR:
315  * There is no event-code assigned to the fixed-mode PMCs.
317  * For a fixed-mode PMC, which has an equivalent event on a general-purpose
318  * PMC, the event-code of the equivalent event is used for the fixed-mode PMC,
321  * For a fixed-mode PMC, which doesn't have an equivalent event, a
322  * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS.
323  * The pseudo event-code for a fixed-mode PMC must be 0x00.
324  * The pseudo umask-code is 0xX. The X equals the index of the fixed
325  * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
338 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
343 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
358  * We model BTS tracing as another fixed-mode PMC.
367  * The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for
386  * There is no event-code assigned to the TopDown events.
390  * For the metric events, the pseudo event-code is 0x00.
391  * The pseudo umask-code starts from the middle of the pseudo event
414 	return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM;  in is_metric_idx()
422 #define INTEL_PMC_OTHER_TOPDOWN_BITS(bit)	\  argument
423 			(~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
439  * We model guest LBR event tracing as another fixed-mode PMC like BTS.
441  * We choose bit 58 because it's used to indicate LBR stack frozen state
442  * for architectural perfmon v4, also we unconditionally mask that bit in
452  * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
453  * since it would claim bit 58 which is effectively Fixed26.
517  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
518  * bit 0 is used to indicate the existence of IBS.
569 #define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
578 static inline int forward_event_to_ibs(struct perf_event *event) { return -ENOENT; }  in forward_event_to_ibs()
589  * EXACT - the IP points to the exact instruction that triggered the
591  * VM    - original X86_VM_MASK; see set_linear_ip().
611  * We abuse bit 3 from flags to pass exact information, see
615 	(regs)->ip = (__ip);					\
616 	(regs)->sp = (unsigned long)__builtin_frame_address(0);	\
617 	(regs)->cs = __KERNEL_CS;				\
618 	regs->flags = 0;					\