Lines Matching +full:vendor +full:- +full:specific

1 /* SPDX-License-Identifier: GPL-2.0 */
29 #define MCG_STATUS_SEAM_NR	BIT_ULL(12)  /* Machine check inside SEAM non-root mode */
49 /* AMD-specific bits */
58  *  - Deferred error interrupt type is specifiable by bank.
59  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
61  *  - TCC bit is present in MCx_STATUS.
72  * We should mask out bit 12 when looking for specific signatures
73  * of uncorrected errors - so the F bit is deliberately skipped
79 #define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
95 #define MCI_ADDR_PHYSADDR	GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)
197  * struct mce_hw_err - Hardware Error Record.
199  * @vendor:	Vendor-specific error information.
201  * Vendor-specific fields should not be added to struct mce. Instead, vendors
202  * should export their vendor-specific data through their structure in the
203  * vendor union below.
205  * AMD's vendor data is parsed by error decoding tools for supplemental error
207  * Only add new fields at the end of AMD's vendor structure.
217 	} vendor;  member
255 					     u64 lapic_id) { return -EINVAL; }  in apei_smca_report_x86_error()