Lines Matching +full:1 +full:c
35 FIXED_EVENT_CONSTRAINT(0x0082, 1), /* unhalted core clock cycles */
42 FIXED_EVENT_CONSTRAINT(0x0082, 1), /* unhalted core clock cycles */
51 [C(L1D)] = {
52 [C(OP_READ)] = {
53 [C(RESULT_ACCESS)] = 0x0042,
54 [C(RESULT_MISS)] = 0x0538,
56 [C(OP_WRITE)] = {
57 [C(RESULT_ACCESS)] = 0x0043,
58 [C(RESULT_MISS)] = 0x0562,
60 [C(OP_PREFETCH)] = {
61 [C(RESULT_ACCESS)] = -1,
62 [C(RESULT_MISS)] = -1,
65 [C(L1I)] = {
66 [C(OP_READ)] = {
67 [C(RESULT_ACCESS)] = 0x0300,
68 [C(RESULT_MISS)] = 0x0301,
70 [C(OP_WRITE)] = {
71 [C(RESULT_ACCESS)] = -1,
72 [C(RESULT_MISS)] = -1,
74 [C(OP_PREFETCH)] = {
75 [C(RESULT_ACCESS)] = 0x030a,
76 [C(RESULT_MISS)] = 0x030b,
79 [C(LL)] = {
80 [C(OP_READ)] = {
81 [C(RESULT_ACCESS)] = -1,
82 [C(RESULT_MISS)] = -1,
84 [C(OP_WRITE)] = {
85 [C(RESULT_ACCESS)] = -1,
86 [C(RESULT_MISS)] = -1,
88 [C(OP_PREFETCH)] = {
89 [C(RESULT_ACCESS)] = -1,
90 [C(RESULT_MISS)] = -1,
93 [C(DTLB)] = {
94 [C(OP_READ)] = {
95 [C(RESULT_ACCESS)] = 0x0042,
96 [C(RESULT_MISS)] = 0x052c,
98 [C(OP_WRITE)] = {
99 [C(RESULT_ACCESS)] = 0x0043,
100 [C(RESULT_MISS)] = 0x0530,
102 [C(OP_PREFETCH)] = {
103 [C(RESULT_ACCESS)] = 0x0564,
104 [C(RESULT_MISS)] = 0x0565,
107 [C(ITLB)] = {
108 [C(OP_READ)] = {
109 [C(RESULT_ACCESS)] = 0x00c0,
110 [C(RESULT_MISS)] = 0x0534,
112 [C(OP_WRITE)] = {
113 [C(RESULT_ACCESS)] = -1,
114 [C(RESULT_MISS)] = -1,
116 [C(OP_PREFETCH)] = {
117 [C(RESULT_ACCESS)] = -1,
118 [C(RESULT_MISS)] = -1,
121 [C(BPU)] = {
122 [C(OP_READ)] = {
123 [C(RESULT_ACCESS)] = 0x0700,
124 [C(RESULT_MISS)] = 0x0709,
126 [C(OP_WRITE)] = {
127 [C(RESULT_ACCESS)] = -1,
128 [C(RESULT_MISS)] = -1,
130 [C(OP_PREFETCH)] = {
131 [C(RESULT_ACCESS)] = -1,
132 [C(RESULT_MISS)] = -1,
135 [C(NODE)] = {
136 [C(OP_READ)] = {
137 [C(RESULT_ACCESS)] = -1,
138 [C(RESULT_MISS)] = -1,
140 [C(OP_WRITE)] = {
141 [C(RESULT_ACCESS)] = -1,
142 [C(RESULT_MISS)] = -1,
144 [C(OP_PREFETCH)] = {
145 [C(RESULT_ACCESS)] = -1,
146 [C(RESULT_MISS)] = -1,
155 [C(L1D)] = {
156 [C(OP_READ)] = {
157 [C(RESULT_ACCESS)] = 0x0568,
158 [C(RESULT_MISS)] = 0x054b,
160 [C(OP_WRITE)] = {
161 [C(RESULT_ACCESS)] = 0x0669,
162 [C(RESULT_MISS)] = 0x0562,
164 [C(OP_PREFETCH)] = {
165 [C(RESULT_ACCESS)] = -1,
166 [C(RESULT_MISS)] = -1,
169 [C(L1I)] = {
170 [C(OP_READ)] = {
171 [C(RESULT_ACCESS)] = 0x0300,
172 [C(RESULT_MISS)] = 0x0301,
174 [C(OP_WRITE)] = {
175 [C(RESULT_ACCESS)] = -1,
176 [C(RESULT_MISS)] = -1,
178 [C(OP_PREFETCH)] = {
179 [C(RESULT_ACCESS)] = 0x030a,
180 [C(RESULT_MISS)] = 0x030b,
183 [C(LL)] = {
184 [C(OP_READ)] = {
185 [C(RESULT_ACCESS)] = 0x0,
186 [C(RESULT_MISS)] = 0x0,
188 [C(OP_WRITE)] = {
189 [C(RESULT_ACCESS)] = 0x0,
190 [C(RESULT_MISS)] = 0x0,
192 [C(OP_PREFETCH)] = {
193 [C(RESULT_ACCESS)] = 0x0,
194 [C(RESULT_MISS)] = 0x0,
197 [C(DTLB)] = {
198 [C(OP_READ)] = {
199 [C(RESULT_ACCESS)] = 0x0568,
200 [C(RESULT_MISS)] = 0x052c,
202 [C(OP_WRITE)] = {
203 [C(RESULT_ACCESS)] = 0x0669,
204 [C(RESULT_MISS)] = 0x0530,
206 [C(OP_PREFETCH)] = {
207 [C(RESULT_ACCESS)] = 0x0564,
208 [C(RESULT_MISS)] = 0x0565,
211 [C(ITLB)] = {
212 [C(OP_READ)] = {
213 [C(RESULT_ACCESS)] = 0x00c0,
214 [C(RESULT_MISS)] = 0x0534,
216 [C(OP_WRITE)] = {
217 [C(RESULT_ACCESS)] = -1,
218 [C(RESULT_MISS)] = -1,
220 [C(OP_PREFETCH)] = {
221 [C(RESULT_ACCESS)] = -1,
222 [C(RESULT_MISS)] = -1,
225 [C(BPU)] = {
226 [C(OP_READ)] = {
227 [C(RESULT_ACCESS)] = 0x0028,
228 [C(RESULT_MISS)] = 0x0029,
230 [C(OP_WRITE)] = {
231 [C(RESULT_ACCESS)] = -1,
232 [C(RESULT_MISS)] = -1,
234 [C(OP_PREFETCH)] = {
235 [C(RESULT_ACCESS)] = -1,
236 [C(RESULT_MISS)] = -1,
239 [C(NODE)] = {
240 [C(OP_READ)] = {
241 [C(RESULT_ACCESS)] = -1,
242 [C(RESULT_MISS)] = -1,
244 [C(OP_WRITE)] = {
245 [C(RESULT_ACCESS)] = -1,
246 [C(RESULT_MISS)] = -1,
248 [C(OP_PREFETCH)] = {
249 [C(RESULT_ACCESS)] = -1,
250 [C(RESULT_MISS)] = -1,
425 struct event_constraint *c; in zhaoxin_get_event_constraints() local
428 for_each_event_constraint(c, x86_pmu.event_constraints) { in zhaoxin_get_event_constraints()
429 if ((event->hw.config & c->cmask) == c->code) in zhaoxin_get_event_constraints()
430 return c; in zhaoxin_get_event_constraints()
472 .apic = 1,
476 .max_period = (1ULL << 47) - 1,
510 struct event_constraint *c; in zhaoxin_pmu_init() local
522 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT - 1) in zhaoxin_pmu_init()
533 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); in zhaoxin_pmu_init()
535 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in zhaoxin_pmu_init()
539 x86_pmu.fixed_cntr_mask64 = GENMASK_ULL(edx.split.num_counters_fixed - 1, 0); in zhaoxin_pmu_init()
546 * Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D] in zhaoxin_pmu_init()
552 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in zhaoxin_pmu_init()
555 x86_pmu.enabled_ack = 1; in zhaoxin_pmu_init()
611 for_each_event_constraint(c, x86_pmu.event_constraints) { in zhaoxin_pmu_init()
612 c->idxmsk64 |= x86_pmu.cntr_mask64; in zhaoxin_pmu_init()
613 c->weight += x86_pmu_num_counters(NULL); in zhaoxin_pmu_init()