232 	union intel_x86_pebs_dse dse;  in precise_store_data()  local
235 	dse.val = status;  in precise_store_data()
244 	if (dse.st_stlb_miss)  in precise_store_data()
254 	if (dse.st_l1d_hit)  in precise_store_data()
262 	if (dse.st_locked)  in precise_store_data()
270 	union perf_mem_data_src dse;  in precise_datala_hsw()  local
272 	dse.val = PERF_MEM_NA;  in precise_datala_hsw()
275 		dse.mem_op = PERF_MEM_OP_STORE;  in precise_datala_hsw()
277 		dse.mem_op = PERF_MEM_OP_LOAD;  in precise_datala_hsw()
289 			dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;  in precise_datala_hsw()
291 			dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;  in precise_datala_hsw()
293 	return dse.val;  in precise_datala_hsw()
315 			       u8 dse, bool tlb, bool lock, bool blk)  in __grt_latency_data()  argument
321 	dse &= PERF_PEBS_DATA_SOURCE_GRT_MASK;  in __grt_latency_data()
322 	val = hybrid_var(event->pmu, pebs_data_source)[dse];  in __grt_latency_data()
336 	union intel_x86_pebs_dse dse;  in grt_latency_data()  local
338 	dse.val = status;  in grt_latency_data()
340 	return __grt_latency_data(event, status, dse.ld_dse,  in grt_latency_data()
341 				  dse.ld_locked, dse.ld_stlb_miss,  in grt_latency_data()
342 				  dse.ld_data_blk);  in grt_latency_data()
348 	union intel_x86_pebs_dse dse;  in cmt_latency_data()  local
350 	dse.val = status;  in cmt_latency_data()
352 	return __grt_latency_data(event, status, dse.mtl_dse,  in cmt_latency_data()
353 				  dse.mtl_stlb_miss, dse.mtl_locked,  in cmt_latency_data()
354 				  dse.mtl_fwd_blk);  in cmt_latency_data()
359 	union intel_x86_pebs_dse dse;  in lnc_latency_data()  local
363 	dse.val = status;  in lnc_latency_data()
370 	if (dse.lnc_stlb_miss)  in lnc_latency_data()
375 	if (dse.lnc_locked)  in lnc_latency_data()
378 	if (dse.lnc_data_blk)  in lnc_latency_data()
380 	if (dse.lnc_addr_blk)  in lnc_latency_data()
382 	if (!dse.lnc_data_blk && !dse.lnc_addr_blk)  in lnc_latency_data()
414 	union intel_x86_pebs_dse dse;  in load_latency_data()  local
417 	dse.val = status;  in load_latency_data()
422 	val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];  in load_latency_data()
432 	pebs_set_tlb_lock(&val, dse.ld_stlb_miss, dse.ld_locked);  in load_latency_data()
445 	if (dse.ld_data_blk)  in load_latency_data()
452 	if (dse.ld_addr_blk)  in load_latency_data()
455 	if (!dse.ld_data_blk && !dse.ld_addr_blk)  in load_latency_data()
463 	union intel_x86_pebs_dse dse;  in store_latency_data()  local
467 	dse.val = status;  in store_latency_data()
472 	val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse];  in store_latency_data()
474 	pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked);  in store_latency_data()
502 	u64 status, dla, dse, lat;  member
514 	u64 status, dla, dse, lat;  member
543 	u64 status, dla, dse, lat;  member
1782 		data->data_src.val = get_data_src(event, pebs->dse);  in setup_pebs_fixed_sample_data()