Lines Matching +full:es +full:- +full:enable

1 /* SPDX-License-Identifier: GPL-2.0 */
9 * head.S contains the 32-bit startup code.
14 * kernel it will end up at 0x1000 + 1Mb I hope so as I assume this. - AC]
33 #include <asm/processor-flags.h>
34 #include <asm/asm-offsets.h>
58 * from startup_32. This is the same as the link-time virtual address of X,
60 * assembler/linker that we do not want the actual run-time address of X. This
61 * prevents the linker from trying to create unwanted run-time relocation
64 * A reference X(%reg) will result in the link-time VA of X being stored with
65 * the instruction, and a run-time R_X86_64_RELATIVE relocation entry that
66 * adds the 64-bit base address where the kernel is loaded.
68 * Replacing it with (X-startup_32)(%reg) results in the offset being stored,
69 * and no run-time relocation.
72 * the run-time address of startup_32 [i.e. rva(X)(%reg)], or as an immediate
79 #define rva(X) ((X) - startup_32)
96 * address we are running at. The reserved chunk of the real-mode
113 movl %eax, %es
127 /* Setup Exception handling for SEV-ES */
143 * for safe in-place decompression.
167 /* Enable PAE mode */
233 /* Enable the boot page tables */
237 /* Enable Long mode in EFER (Extended Feature Enable Register) */
250 /* Check if the C-bit position is correct when SEV is active */
296 movl %eax, %es
310 * We cannot rely on the calculation done in 32-bit mode, since we
311 * may have been invoked via the 64-bit entry point.
316 leaq startup_32(%rip) /* - $startup_32 */, %rbp
337 * At this point we are in long mode with 4-level paging enabled,
338 * but we might want to enable 5-level paging or vice versa.
345 * 4- to 5-level paging for cases when the bootloader puts the kernel
346 * above 4G, but didn't enable 5-level paging for us.
348 * The same trampoline can be used to switch from 5- to 4-level paging
349 * mode, like when starting 4-level paging kernel via kexec() when
350 * original kernel worked in 5-level paging mode.
353 * memory as we don't have a way to load 64-bit values into CR3 in
354 * 32-bit mode.
357 /* Make sure we have GDT with 32-bit code segment */
381 * CPUID instructions can be properly handled for SEV-ES guests.
383 * For SEV-SNP, the CPUID table also needs to be set up in advance of any
385 * sev_enable(), which will also handle the rest of the SEV-related
400 * a trampoline in 32-bit addressable memory if the current number does
419 leaq (_bss-8)(%rip), %rsi
420 leaq rva(_bss-8)(%rbx), %rdi
421 movl $(_bss - startup_32), %ecx
480 /* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */
491 .word gdt_end - gdt - 1
492 .quad gdt - gdt64
496 .word gdt_end - gdt - 1
507 .word boot_idt_end - boot_idt - 1