Lines Matching +full:carry +full:- +full:less
1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sparc64/math-emu/math.c
8 * Emulation routines originate from soft-fp package, which is part
22 #include "sfp-util_64.h"
23 #include <math-emu/soft-fp.h>
24 #include <math-emu/single.h>
25 #include <math-emu/double.h>
26 #include <math-emu/quad.h>
28 /* QUAD - ftt == 3 */
46 /* SUBNORMAL - ftt == 2 */
64 #define FXTOS 0x084 /* Only Ultra-III generates this. */
65 #define FXTOD 0x088 /* Only Ultra-III generates this. */
67 #define FITOS 0x0c4 /* Only Ultra-III generates this. */
69 #define FITOD 0x0c8 /* Only Ultra-III generates this. */
103 u64 fsr = current_thread_info()->xfsr[0]; in record_exception()
112 if((eflag & (eflag - 1)) != 0) { in record_exception()
148 current_thread_info()->xfsr[0] = fsr; in record_exception()
154 regs->tpc = regs->tnpc; in record_exception()
155 regs->tnpc += 4; in record_exception()
169 unsigned long pc = regs->tpc; in do_mathemu()
170 unsigned long tstate = regs->tstate; in do_mathemu()
174 whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack) in do_mathemu()
175 non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */ in do_mathemu()
192 if (get_user(insn, (u32 __user *) pc) != -EFAULT) { in do_mathemu()
195 /* QUAD - ftt == 3 */ in do_mathemu()
215 * for these cases. Pre-Niagara systems generate in do_mathemu()
220 unsigned long x = current_thread_info()->xfsr[0]; in do_mathemu()
228 unsigned long x = current_thread_info()->xfsr[0]; in do_mathemu()
235 /* SUBNORMAL - ftt == 2 */ in do_mathemu()
252 /* Only Ultra-III generates these */ in do_mathemu()
273 XR = current_thread_info()->xfsr[0] >> 10; in do_mathemu()
275 XR = current_thread_info()->xfsr[0] >> (30 + ((insn >> 10) & 0x6)); in do_mathemu()
281 case 2: if (XR == 1 || XR == 2) IR = 1; break; /* Less or Greater */ in do_mathemu()
282 case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */ in do_mathemu()
283 case 4: if (XR == 1) IR = 1; break; /* Less */ in do_mathemu()
294 XR = regs->tstate >> 32; in do_mathemu()
303 case 2: if ((XR & 4) || freg) IR = 1; break; /* Less or Equal */ in do_mathemu()
304 case 3: if (freg) IR = 1; break; /* Less */ in do_mathemu()
305 case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */ in do_mathemu()
306 case 5: if (XR & 1) IR = 1; break; /* Carry Set */ in do_mathemu()
323 XR = regs->u_regs[freg]; in do_mathemu()
324 else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) { in do_mathemu()
327 win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP])); in do_mathemu()
328 get_user(XR, &win32->locals[freg - 16]); in do_mathemu()
332 win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS); in do_mathemu()
333 get_user(XR, &win->locals[freg - 16]); in do_mathemu()
338 case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */ in do_mathemu()
339 case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */ in do_mathemu()
347 current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK); in do_mathemu()
348 regs->tpc = regs->tnpc; in do_mathemu()
349 regs->tnpc += 4; in do_mathemu()
361 /* Starting with UltraSPARC-T2, the cpu does not set the FP Trap in do_mathemu()
368 int ftt = (current_thread_info()->xfsr[0] >> 14) & 0x7; in do_mathemu()
372 current_thread_info()->xfsr[0] &= ~0x1c000; in do_mathemu()
376 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; in do_mathemu()
380 case 1: rs1 = (argp)&f->regs[freg]; in do_mathemu()
382 if (!(current_thread_info()->fpsaved[0] & flags)) in do_mathemu()
394 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; in do_mathemu()
398 case 1: rs2 = (argp)&f->regs[freg]; in do_mathemu()
400 if (!(current_thread_info()->fpsaved[0] & flags)) in do_mathemu()
412 current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */; in do_mathemu()
416 case 1: rd = (argp)&f->regs[freg]; in do_mathemu()
418 if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) { in do_mathemu()
419 current_thread_info()->fpsaved[0] = FPRS_FEF; in do_mathemu()
420 current_thread_info()->gsr[0] = 0; in do_mathemu()
422 if (!(current_thread_info()->fpsaved[0] & flags)) { in do_mathemu()
424 memset(f->regs, 0, 32*sizeof(u32)); in do_mathemu()
426 memset(f->regs+32, 0, 32*sizeof(u32)); in do_mathemu()
428 current_thread_info()->fpsaved[0] |= flags; in do_mathemu()
436 /* - */ in do_mathemu()
457 case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break; in do_mathemu()
458 case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break; in do_mathemu()
459 case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break; in do_mathemu()
468 case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break; in do_mathemu()
469 case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break; in do_mathemu()
470 /* Only Ultra-III generates these */ in do_mathemu()
471 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; in do_mathemu()
472 case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break; in do_mathemu()
474 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_mathemu()
476 case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break; in do_mathemu()
496 case 0: xfsr = current_thread_info()->xfsr[0]; in do_mathemu()
497 if (XR == -1) XR = 2; in do_mathemu()
505 current_thread_info()->xfsr[0] = xfsr; in do_mathemu()
507 case 1: rd->s = IR; break; in do_mathemu()
508 case 2: rd->d = XR; break; in do_mathemu()
519 current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK); in do_mathemu()
520 regs->tpc = regs->tnpc; in do_mathemu()
521 regs->tnpc += 4; in do_mathemu()