Lines Matching +full:get +full:- +full:only

1 /* SPDX-License-Identifier: GPL-2.0 */
6 	 * We pass the AFAR in as-is, and we encode the status
7 	 * information as described in asm-sparc64/sfafsr.h
18 	ldxa		[%g0] ASI_AFSR, %g4	! Get AFSR
21 	 * UDBE_CE in %g1.  It only clears ESTATE_ERR_CE in the ESTATE
25 	ldxa		[%g0] ASI_AFAR, %g5	! Get AFAR
40 	 * error bits as-needed.  We only clear them if the UE bit is
41 	 * set.  Likewise, __spitfire_cee_trap below will only do so
44 	 * NOTE: UltraSparc-I/II have high and low UDB error
46 	 *       present on those chips.  UltraSparc-IIi only
105 	.size		__spitfire_access_error,.-__spitfire_access_error
112 	 * 1) single-bit ECC errors during UDB reads to system
114 	 * 2) data parity errors during write-back events
117 	 * only for correctable errors during memory read accesses by
118 	 * the front-end of the processor.
120 	 * The code below is only for trap level 1 CEE events, as it
121 	 * is the only situation where we can safely record and log.
135 	ldxa		[%g0] ASI_AFSR, %g4	! Get AFSR
142 	/* Ok, in this case we only have a correctable error.
143 	 * Indicate we only wish to capture that state in register
144 	 * %g1, and we only disable CE error reporting unlike UE
155 	.size		__spitfire_cee_trap,.-__spitfire_cee_trap
163 	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR
164 	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR
183 	.size		__spitfire_data_access_exception_tl1,.-__spitfire_data_access_exception_tl1
191 	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR
192 	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR
203 	.size		__spitfire_data_access_exception,.-__spitfire_data_access_exception
210 	ldxa		[%g3] ASI_IMMU, %g4	! Get SFSR
222 	.size		__spitfire_insn_access_exception_tl1,.-__spitfire_insn_access_exception_tl1
229 	ldxa		[%g3] ASI_IMMU, %g4	! Get SFSR
241 	.size		__spitfire_insn_access_exception,.-__spitfire_insn_access_exception