Lines Matching full:sbus
3 * sbus.c: UltraSparc SBUS controller support.
40 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
156 /* SBUS Slot 0 --> 3, level 1 --> 7 */
227 * the right ICLR register based upon the lower SBUS irq level in sbus_build_irq()
414 #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
415 #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
417 #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
418 #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
449 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n", in sysio_sbus_error_handler()
463 printk("SYSIO[%x]: Secondary SBUS errors [", portid); in sysio_sbus_error_handler()
524 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n", in sysio_register_error_handlers()
536 control |= 0x100UL; /* SBUS Error Interrupt Enable */ in sysio_register_error_handlers()
589 /* The SYSIO SBUS control register is used for dummy reads in sbus_iommu_init()
669 for_each_node_by_name(dp, "sbus") { in sbus_init()