Lines Matching +full:iommu +full:- +full:map +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0
42 volatile int pci_poke_cpu = -1;
63 pci_poke_cpu = -1;
85 pci_poke_cpu = -1;
107 pci_poke_cpu = -1;
128 pci_poke_cpu = -1;
147 pci_poke_cpu = -1;
166 pci_poke_cpu = -1;
202 /* The of_device layer has translated all of the assigned-address properties
214 addrs = of_get_property(node, "assigned-addresses", &proplen);
220 op_res = &op->resource[0];
221 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
232 op_res->start, op_res->end, i);
235 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
236 } else if (i == dev->rom_base_reg) {
237 res = &dev->resource[PCI_ROM_RESOURCE];
243 res->start = op_res->start;
244 res->end = op_res->end;
245 res->flags = flags;
246 res->name = pci_name(dev);
252 static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
257 sd->iommu = iommu;
258 sd->stc = stc;
259 sd->host_controller = host_controller;
260 sd->op = op;
261 sd->numa_node = numa_node;
278 sd = &dev->dev.archdata;
279 pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
280 pbm->numa_node);
281 sd = &op->dev.archdata;
282 sd->iommu = pbm->iommu;
283 sd->stc = &pbm->stc;
284 sd->numa_node = pbm->numa_node;
293 dev->sysdata = node;
294 dev->dev.parent = bus->bridge;
295 dev->dev.bus = &pci_bus_type;
296 dev->dev.of_node = of_node_get(node);
297 dev->devfn = devfn;
298 dev->multifunction = 0; /* maybe a lie? */
302 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
303 dev->device = of_getintprop_default(node, "device-id", 0xffff);
304 dev->subsystem_vendor =
305 of_getintprop_default(node, "subsystem-vendor-id", 0);
306 dev->subsystem_device =
307 of_getintprop_default(node, "subsystem-id", 0);
309 dev->cfg_size = pci_cfg_space_size(dev);
318 dev->class = class >> 8;
319 dev->revision = class & 0xff;
321 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
322 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
328 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
331 dev->current_state = PCI_UNKNOWN; /* unknown power state */
332 dev->error_state = pci_channel_io_normal;
333 dev->dma_mask = 0xffffffff;
336 /* a PCI-PCI bridge */
337 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
338 dev->rom_base_reg = PCI_ROM_ADDRESS1;
340 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
342 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
343 dev->rom_base_reg = PCI_ROM_ADDRESS;
345 dev->irq = sd->op->archdata.irqs[0];
346 if (dev->irq == 0xffffffff)
347 dev->irq = PCI_IRQ_NONE;
351 dev->vendor, dev->device, dev->hdr_type, dev->class);
353 pci_parse_of_addrs(sd->op, node, dev);
363 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
370 if ((map & (1 << idx)) != 0) {
392 u8 map;
394 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
395 apb_calc_first_last(map, &first, &last);
396 res = bus->resource[0];
397 res->flags = IORESOURCE_IO;
399 region.end = (last << 21) + ((1 << 21) - 1);
400 pcibios_bus_to_resource(dev->bus, res, ®ion);
402 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
403 apb_calc_first_last(map, &first, &last);
404 res = bus->resource[1];
405 res->flags = IORESOURCE_MEM;
407 region.end = (last << 29) + ((1 << 29) - 1);
408 pcibios_bus_to_resource(dev->bus, res, ®ion);
432 /* parse bus-range property */
433 busrange = of_get_property(node, "bus-range", &len);
435 pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
441 pci_info(dev, " Bridge bus range [%u --> %u]\n",
452 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
459 bus->primary = dev->bus->number;
461 bus->bridge_ctl = 0;
468 /* PCI #address-cells == 3 and #size-cells == 2 always */
469 res = &dev->resource[PCI_BRIDGE_RESOURCES];
470 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
471 res->flags = 0;
472 bus->resource[i] = res;
483 for (; len >= 32; len -= 32, ranges += 8) {
497 /* On PCI-Express systems, PCI bridges that have no devices downstream
498 * have a bogus size value where the first 32-bit cell is 0xffffffff.
508 res = bus->resource[0];
509 if (res->flags) {
515 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
520 res = bus->resource[i];
524 res->flags = flags;
526 region.end = region.start + size - 1;
532 pcibios_bus_to_resource(dev->bus, res, ®ion);
535 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
536 bus->number);
538 pci_info(dev, " bus name: %s\n", bus->name);
554 node, bus->number);
556 prev_devfn = -1;
580 pci_info(dev, "dev header type: %x\n", dev->hdr_type);
594 dp = pdev->dev.of_node;
607 list_for_each_entry(dev, &bus->devices, bus_list) {
615 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
618 list_for_each_entry(child_bus, &bus->children, node)
627 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
634 p->name = "Video RAM area";
635 p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
639 pcibios_bus_to_resource(dev->bus, p, ®ion);
650 p, conflict->name, conflict);
666 list_for_each_entry(dev, &bus->devices, bus_list) {
671 if (r->parent || !r->start || !r->flags)
684 list_for_each_entry(child_bus, &bus->children, node)
692 struct device_node *node = pbm->op->dev.of_node;
697 pci_add_resource_offset(&resources, &pbm->io_space,
698 pbm->io_offset);
699 pci_add_resource_offset(&resources, &pbm->mem_space,
700 pbm->mem_offset);
701 if (pbm->mem64_space.flags)
702 pci_add_resource_offset(&resources, &pbm->mem64_space,
703 pbm->mem64_offset);
704 pbm->busn.start = pbm->pci_first_busno;
705 pbm->busn.end = pbm->pci_last_busno;
706 pbm->busn.flags = IORESOURCE_BUS;
707 pci_add_resource(&resources, &pbm->busn);
708 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
725 int pcibios_enable_device(struct pci_dev *dev, int mask)
736 if (!(mask & (1<<i)))
739 if (res->flags & IORESOURCE_IO)
741 if (res->flags & IORESOURCE_MEM)
746 pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
755 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
759 return -EINVAL;
761 vma->vm_pgoff += (ioaddr + pbm->io_space.start) >> PAGE_SHIFT;
769 struct pci_pbm_info *pbm = pbus->sysdata;
771 return pbm->numa_node;
780 struct pci_pbm_info *pbm = pbus->sysdata;
784 ret = -ENXIO;
786 ret = pbm->index;
796 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
799 if (!pbm->setup_msi_irq)
800 return -EINVAL;
802 return pbm->setup_msi_irq(&irq, pdev, desc);
809 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
811 if (pbm->teardown_msi_irq)
812 pbm->teardown_msi_irq(irq, pdev);
816 /* ALI sound chips generate 31-bits of DMA, a special register
821 struct iommu *iommu = dev->archdata.iommu;
828 if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
829 to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
838 if (iommu->dma_addr_mask & 0x80000000)
860 pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
878 if (dev->is_virtfn) {
881 pdev = dev->physfn;
882 psd = &pdev->dev.archdata;
883 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
884 psd->stc, psd->host_controller, NULL,
885 psd->numa_node);
907 list_for_each_entry(pdev, &pbus->devices, bus_list) {
913 slot_num = of_get_property(pdev->dev.of_node,
914 "physical-slot#", &len);
927 list_for_each_entry(bus, &pbus->children, node)
939 u32 mask;
941 prop = of_get_property(node, "slot-names", &len);
945 mask = prop->slot_mask;
946 sp = prop->names;
949 pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
950 node, mask);
953 while (mask) {
957 if (!(mask & this_bit)) {
971 mask &= ~this_bit;
984 pdev = list_first_entry(&pbus->devices, struct pci_dev,
991 if (pbus->self) {
993 /* PCI->PCI bridge */
994 node = pbus->self->dev.of_node;
997 struct pci_pbm_info *pbm = pbus->sysdata;
1000 node = pbm->op->dev.of_node;