Lines Matching full:g1
96 rdpr %pstate, %g1
97 andn %g1, PSTATE_AM, %g1
98 wrpr %g1, 0x0, %pstate
323 sethi %hi(prom_root_compatible), %g1
324 or %g1, %lo(prom_root_compatible), %g1
329 ldub [%g1], %g4
335 add %g1, 1, %g1
337 sethi %hi(is_sun4v), %g1
338 or %g1, %lo(is_sun4v), %g1
340 stw %g7, [%g1]
386 sethi %hi(prom_cpu_compatible), %g1
387 or %g1, %lo(prom_cpu_compatible), %g1
392 ldub [%g1], %g4
398 add %g1, 1, %g1
402 89: sethi %hi(prom_cpu_compatible), %g1
403 or %g1, %lo(prom_cpu_compatible), %g1
408 ldub [%g1], %g4
414 add %g1, 1, %g1
416 sethi %hi(prom_cpu_compatible), %g1
417 or %g1, %lo(prom_cpu_compatible), %g1
418 ldub [%g1 + 6], %g2
427 70: ldub [%g1 + 7], %g2
452 91: sethi %hi(prom_cpu_compatible), %g1
453 or %g1, %lo(prom_cpu_compatible), %g1
454 ldub [%g1 + 17], %g2
464 sethi %hi(prom_cpu_compatible), %g1
465 or %g1, %lo(prom_cpu_compatible), %g1
470 ldub [%g1], %g4
476 add %g1, 1, %g1
487 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
488 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
489 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
499 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
500 wr %g1, %asr18
530 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
531 stxa %g1, [%g0] ASI_LSU_CONTROL
552 BRANCH_IF_SUN4V(g1, sun4v_init)
577 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
583 sethi %hi(tlb_type), %g1
584 stw %g2, [%g1 + %lo(tlb_type)]
587 sethi %hi(sun4v_chip_type), %g1
588 lduw [%g1 + %lo(sun4v_chip_type)], %g1
589 cmp %g1, SUN4V_CHIP_NIAGARA1
591 cmp %g1, SUN4V_CHIP_NIAGARA2
594 cmp %g1, SUN4V_CHIP_NIAGARA3
597 cmp %g1, SUN4V_CHIP_NIAGARA4
600 cmp %g1, SUN4V_CHIP_NIAGARA5
603 cmp %g1, SUN4V_CHIP_SPARC_M6
606 cmp %g1, SUN4V_CHIP_SPARC_M7
609 cmp %g1, SUN4V_CHIP_SPARC_M8
612 cmp %g1, SUN4V_CHIP_SPARC_SN
678 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
682 1: sethi %hi(tlb_type), %g1
683 stw %g2, [%g1 + %lo(tlb_type)]
698 sethi %hi(tlb_type), %g1
699 stw %g2, [%g1 + %lo(tlb_type)]
707 mov 1, %g1
708 sllx %g1, THREAD_SHIFT, %g1
709 sub %g1, (STACKFRAME_SZ + STACK_BIAS + TRACEREG_SZ), %g1
710 add %g6, %g1, %sp
827 mov PRIMARY_CONTEXT, %g1
829 661: stxa %g2, [%g1] ASI_DMMU
832 stxa %g2, [%g1] ASI_MMU