Lines Matching +full:diag +full:- +full:version
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
37 /* SPARCstation-5: only 6 bits are decoded. */
69 /* Block-copy operations are available only on certain V8 cpus. */
79 /* Block-fill operations are available on certain V8 cpus */
83 * the available ASI's for physical ram pass-through, but I don't have
89 #define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
90 #define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
91 #define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
92 #define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
137 #define ASI_PL 0x88 /* Primary, implicit, l-endian */
138 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */
139 #define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
140 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
143 * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
145 * ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4
148 #define ASI_MCD_PRIV_PRIMARY 0x02 /* (NG7) Privileged MCD version VA */
149 #define ASI_MCD_REAL 0x05 /* (NG7) Privileged MCD version PA */
150 #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
151 #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
154 #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
155 #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
156 #define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
157 #define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */
160 #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
166 #define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */
167 #define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
168 #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
169 #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
170 #define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
171 #define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
173 #define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
174 #define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
175 #define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
176 #define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */
177 #define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */
184 #define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
185 #define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
188 #define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */
189 #define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */
190 #define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */
191 #define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
193 #define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */
194 #define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/
201 #define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
204 #define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */
205 #define ASI_IMMU 0x50 /* Insn-MMU main register space */
206 #define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
207 #define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
208 #define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
209 #define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
210 #define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
211 #define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
212 #define ASI_DMMU 0x58 /* Data-MMU main register space */
213 #define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
214 #define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
215 #define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
216 #define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
217 #define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
218 #define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
219 #define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
224 #define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
225 #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
227 #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
228 #define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */
229 #define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/
233 #define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */
234 #define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */
235 #define ASI_EC_W 0x76 /* E-cache diag write access */
243 #define ASI_EC_R 0x7e /* E-cache diag read access */
250 #define ASI_MCD_PRIMARY 0x90 /* (NG7) MCD version load/store */
254 #define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
255 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
256 #define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
257 #define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */
258 #define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
259 #define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
260 #define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */
261 #define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */
262 #define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */
263 #define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */
264 #define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */
265 #define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */
266 #define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
267 #define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
268 #define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
269 #define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
270 #define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */
271 #define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
272 #define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */
273 #define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
276 #define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
279 #define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load,
284 #define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load,
285 * Most-Recently-Used, primary,
288 #define ASI_ST_BLKINIT_MRU_S 0xf3 /* (NG4) init-store, twin load,
289 * Most-Recently-Used, secondary,
294 #define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load,
295 * Most-Recently-Used, primary,
296 * implicit, little-endian
298 #define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load,
299 * Most-Recently-Used, secondary,
300 * implicit, little-endian