Lines Matching +full:real +full:- +full:time
1 /* SPDX-License-Identifier: GPL-2.0 */
16 * -----------------------------------------------
23 * -----------------------------------------------
25 * The second type are "hyper-fast traps" which encode the function
27 * numbers > 0x80. The register usage for hyper-fast traps is as
30 * -----------------------------------------------
36 * -----------------------------------------------
44 * defined below. So, for example, if a hyper-fast trap takes
49 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
63 #define HV_ENORADDR 2 /* Invalid real address */
91 * state. The 64-bit exit code may be passed to a service entity as
99 * the guest code. A non-zero exit code denotes a guest specific
119 * HV_ENORADDR Buffer is to an illegal real address.
124 * by the real address in ARG0. The buffer provided must be 16 byte
148 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
164 * RET1: time remaining in milliseconds
170 * to guest termination within a bounded time period. The platform action
175 * implementated granularity is given by the 'watchdog-resolution'
178 * 'watchdog-max-timeout' property of the 'platform' node.
185 * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
189 * The 'time remaining' return value is valid regardless of whether the
190 * return status is EOK or EINVAL. A non-zero return value indicates the
193 * watchdog timer was disabled at the time of the call, the return value is
199 * 'time remaining' return value may be larger than the previously requested
205 * re-enabled upon returning to normal execution. The API has been designed
206 * with this in mind, and the 'time remaining' result of the disable call may
207 * be used directly as the timeout argument of the re-enable call.
225 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
228 * array in real memory, of which each 16-bit word is a CPU ID. CPU
230 * the number of entries (16-bit words) in the CPU list, and the
231 * second is the (real address) pointer to the CPU ID list.
244 * ENORADDR Invalid PC or RTBA real address
248 * Start CPU with given CPU ID with PC in %pc and with a real trap
296 * an interrupt (device, %stick_compare, or cross-call) is targeted to
314 * invoked the cpu-yield service, that vCPU will be resumed.
315 * Poke interrupts may only be sent to valid, non-local CPUs.
328 * ARG1: base real address
331 * ERRORS: ENORADDR Invalid base real address
334 * EBADALIGN Base real address is not correctly aligned
337 * Configure the given queue to be placed at the given base real
339 * must be a power of 2. The base real address must be aligned
342 * byte real address boundary.
351 * ----- -------------------------
355 * 0x3f non-resumable error queue
377 * RET1: base real address
381 * Return the configuration info for the given queue. The base real
387 * base real address returned is undefined.
394 * ARG0-1: CPU list
395 * ARG2: data real address
397 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
398 * is not 2-byte aligned.
409 * 64-bytes at the given data real address. The data must be 64-byte
462 * ERRORS: ENORADDR Invalid RTBA real address
465 * Set the real trap base address of the local cpu to the given RTBA.
536 * The fault status block is a multiple of 64-bytes and must be aligned
537 * on a 64-byte boundary.
575 /* Values 16 --> -2 are reserved. */
576 #define HV_FAULT_TYPE_MULTIPLE -1
593 * ENORADDR Invalid real address in TTE
595 * Create a non-permanent mapping using the given TTE, virtual
632 * to an 8-byte boundary, or TSB base
649 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
668 * non-zero contexts. The TSB descriptions pointer is a pointer to an
686 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
707 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
709 * Demaps all non-permanent virtual page mappings previously specified
727 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
729 * Demaps all non-permanent virtual page mappings previously specified
753 * ENORADDR Invalid real address in TTE
779 * ARG0: real address
781 * RET1: previous mmu fault area real address
782 * ERRORS: ENORADDR Invalid real address
785 * Configure the MMU fault status area for the calling CPU. A 64-byte
786 * aligned real address specifies where MMU fault status information
788 * for the first invocation. Specifying a fault area at real address
799 * ERRORS: ENORADDR Invalid real address when disabling
809 * translation is disabled, any non-zero value will enable
814 * target address is a virtual address else it is a real address.
849 * ENORADDR Invalid real address for buffer pointer
870 * ENORADDR Invalid real address for buffer pointer
886 * RET1: fault area real address
890 * CPU. The real address of the fault status area is returned in
904 * ARG0: real address
908 * ERRORS: ENORADDR Invalid real address
913 * Zero the memory contents in the range real address to real address
915 * memory address range. Scrubbing is started at the given real
919 * The real address and length must be aligned on an 8K boundary, or
924 * error reported via a resumable or non-resumable trap. The second
925 * use requires the arguments to be equal to the real address and length
933 * ARG0: real address
937 * ERRORS: ENORADDR Invalid real address
942 * Force the next access within the real address to real address plus
945 * returned in RET1. The real address and length must be aligned on
952 * M7 and later processors provide an on-chip coprocessor which
978 * ETOOMANY too many ccbs with all-or-nothing flag
983 * time (check status data)
985 * 0 - exact CCB could not be executed
986 * 1 - CCB opcode cannot be executed
987 * 2 - CCB version cannot be executed
988 * 3 - vcpu cannot execute CCBs
989 * 4 - no CCBs can be executed
1020 * ARG0: real address of CCB completion area
1023 * - RET1[0]: CCB state
1024 * - RET1[1]: dax unit
1025 * - RET1[2]: queue number
1026 * - RET1[3]: queue position
1058 * ARG0: real address of CCB completion area
1083 /* Time of day services.
1085 * The hypervisor maintains the time of day on a per-domain basis.
1086 * Changing the time of day in one domain does not affect the time of
1089 * Time is described by a single unsigned 64-bit word which is the
1102 * Return the current time of day. May block if TOD access is
1108 unsigned long sun4v_tod_get(unsigned long *time);
1119 * The current time of day is set to the value specified in ARG0. May
1125 unsigned long sun4v_tod_set(unsigned long time);
1142 * A virtual BREAK is represented by the 64-bit value -1.
1144 * A virtual HUP signal is represented by the 64-bit value -2.
1158 * invalid except for the 64-bit value -1 which is used to send a
1166 * ARG0: buffer real address
1178 * A virtual BREAK is represented by the 64-bit RET1 value -1.
1180 * A virtual HUP signal is represented by the 64-bit RET1 value -2.
1189 * ARG0: buffer real address
1220 * valid real address
1233 * The software state description argument is a real address of a data buffer
1234 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
1235 * terminated 7-bit ASCII string of up to 31 characters not including the
1254 * valid real address
1268 * ARG1: buffer real address
1283 * ARG1: buffer real address
1342 * round-robin trap trace queue within which the hypervisor writes
1343 * 64-byte entries detailing hyperprivileged traps taken n behalf of
1347 * The trap trace control structure is 64-bytes long and placed at the
1362 * in the trap-trace buffer. The tail offset is the offset of the
1373 unsigned char hpstate; /* Hyper-privileged state */
1409 * ARG0: real address
1413 * ERRORS: ENORADDR Invalid real address
1415 * EBADALIGN Real address not aligned on 64-byte boundary
1418 * trace buffer to the hypervisor. The real address supplies the real
1419 * base address of the trap trace queue and must be 64-byte aligned.
1422 * sized for a power of two number of 64-byte trap trace entries plus
1423 * an initial 64-byte control structure.
1428 * If the real address is illegal or badly aligned, then trap tracing
1441 * RET1: real address
1445 * Returns the size and location of the previously declared trap-trace
1462 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1463 * tracing - which will ensure future compatibility.
1476 * state in RET1. A guest should pass a non-zero value to freeze and
1484 * ARG0: tag (16-bits)
1493 * is modified - none of the other registers holding arguments are
1516 * ARG0: real address
1520 * ERRORS: ENORADDR Invalid real address
1521 * EBADALIGN Real address is not aligned on a 64-byte
1523 * EINVAL Size is non-zero but less than minimum size
1528 * Declare a domain dump buffer to the hypervisor. The real address
1529 * provided for the domain dump buffer must be 64-byte aligned. The
1537 * "snapshots" of any dump-buffer information. Each call to
1541 * A specified size of 0 unconfigures the dump buffer. If the real
1554 * RET1: real address of current dump buffer
1575 * consistes of the lower 28-bits of the hi-cell of the
1585 * "interrupts" property or "interrupt-map" property
1588 * sysino System interrupt number. A 64-bit unsigned interger
1843 * tsbnum TSB number. Indentifies which io-tsb is used.
1850 * tsbid A 64-bit aligned data structure which contains
1858 * of the attritbute bits are stores in a 64-bit
1861 * r_addr 64-bit real address
1865 * A PCI device address ia a 32-bit unsigned integer
1882 * or failed. 0 means no error, non-0 means some error
1890 * a real address.
1894 * "size based byte swap" - Some functions do size based byte swapping
1898 * IO bus. Size-based byte swapping converts a
1899 * multi-byte field between big-endian and
1900 * little-endian format.
1929 * EBADALIGN Improperly aligned real address
1930 * ENORADDR Invalid real address
1956 * demap an entry before re-mapping it.
1995 * RET2: real address
2012 * ARG1: real address
2017 * ENORADDR Invalid real address
2021 * for the given real address and attributes. Return the IO address in RET1
2049 * If an error occurs during the read, set RET1 to a non-zero value. The
2075 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
2088 * ARG1: real address
2094 * EBADALIGN Improperly aligned real address
2095 * ENORADDR Bad real address
2098 * Attempt to read the IO address given by the given devhandle, real address,
2102 * non-zero value in RET1. If the read was successful, return zero in RET1
2106 * Non-significant bits in RET2 are not guaranteed to have any specific value
2107 * and therefore must be ignored. If RET1 is returned as non-zero, the data
2110 * The caller must have permission to read from the given devhandle, real
2111 * address, which must be an IO address. The argument real address must be a
2123 * ARG1: real address
2130 * EBADALIGN Improperly aligned real address
2131 * ENORADDR Bad real address
2136 * real address, and size. Size must be 1, 2, 4, or 8. The write is
2141 * error report, but return a non-zero value in RET1. If the write was
2153 * The caller must have permission to write to the given devhandle, real
2154 * address, which must be an IO address. The argument real address must be a
2167 * ARG1: real address
2173 * ENORADDR Bad real address
2175 * Synchronize a memory region described by the given real address and size,
2183 * function with updated real address and size arguments until the entire
2219 * ARG2: real address
2223 * EBADALIGN Improperly aligned real address
2224 * ENORADDR Bad real address
2227 * and to be placed at the given real address and be of the given
2228 * number of entries. The real address must be aligned exactly to match
2229 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
2230 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
2231 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
2245 * RET1: real address
2252 * If the queue is unconfigured, the real address is undefined and the
2266 * Get the valid state of the MSI-EQ described by the given devhandle and
2281 * Set the valid state of the MSI-EQ described by the given devhandle and
2295 * Get the state of the MSI-EQ described by the given devhandle and
2310 * Set the state of the MSI-EQ described by the given devhandle and
2324 * Get the current MSI EQ queue head for the MSI-EQ described by the
2339 * Set the current MSI EQ queue head for the MSI-EQ described by the
2353 * Get the current MSI EQ queue tail for the MSI-EQ described by the
2504 * A 32-bit aligned list of pci_devices.
2507 * real address of a pci_device_list. 32-bit aligned.
2515 * io_page_list A 64-bit aligned list of real addresses. Each real
2519 * io_page_list_p Real address of an io_page_list, 64-bit aligned.
2524 * a pagesize and table size supported by the un-derlying
2527 * Each IOTTE in an IOTSB maps one pagesize-sized page.
2535 * iotsb_index Zero-based IOTTE number within an IOTSB.
2556 * ENORADDR r_addr is not a valid real address
2573 * If successful, the opaque 64-bit handle iotsb_handle is returned in ret1.
2599 * table. However, the table base address r_addr may contain the value -1 which
2677 * the iommu-address-ranges property in the root complex device node defined
2710 * The io_page_list_p specifies the real address of the 64-bit-aligned list of
2712 * real address of a page to be mapped in the IOTSB. The first entry in the I/O
2713 * page list contains the real address of the first page, the 2nd entry for the
2728 * It is implementation-defined whether I/O page real address validity checking
2729 * is done at time mappings are established or deferred until they are
2758 * It is implementation-defined whether I/O page real address validity checking
2759 * is done at time mappings are established or deferred until they are
2804 * Upon success, the real address of the mapping shall be returned in
2848 * ARG1: real address base of queue
2853 * given channel ID, to be placed at the given real address, and
2855 * The real address base of the queue must be aligned on the queue
2856 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2857 * queue must be aligned on a 2048 byte real address boundary.
2863 * The endpoint's transmit queue is un-configured if num entries is zero.
2872 * to reconfiguring it, or un-configuring it. Re or un-configuring of a
2873 * non-empty transmit queue behaves exactly as defined above, however it
2875 * will be delivered prior to the re-configuration taking effect.
2887 * RET1: real address base of queue
2891 * defined by the given channel ID. The real address is the currently
2892 * defined real address base of the defined queue, and num entries is the
2897 * entries set to zero and the real address will have an undefined value.
2942 * ARG1: real address base of queue
2947 * given channel ID, to be placed at the given real address, and
2949 * The real address base of the queue must be aligned on the queue
2950 * size. Each queue entry is 64-bytes, so for example, a 32 entry
2951 * queue must be aligned on a 2048 byte real address boundary.
2953 * The endpoint's transmit queue is un-configured if num entries is zero.
2979 * RET1: real address base of queue
2983 * defined by the given channel ID. The real address is the currently
2984 * defined real address base of the defined queue, and num entries is the
2989 * entries set to zero and the real address will have an undefined value.
3029 * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
3061 * ARG1: table real address
3065 * Register the MTE table at the given table real address, with the
3076 * RET1: table real address
3092 * ARG2: target real address
3093 * ARG3: local real address
3110 * RET1: real address
3118 * ARG0: real address
3302 * ARG0: real address
3304 * RET1: real address
3305 * ERRORS: ENORADDR Invalid real address
3306 * EBADALIGN Real address not aligned on 64-byte boundary
3309 * Enable MMU statistic gathering using the buffer at the given real
3310 * address on the current virtual CPU. The new buffer real address
3311 * is given in ARG1, and the previously specified buffer real address
3314 * If the passed in real address argument is zero, this will disable
3327 * RET1: real address
3330 * Return the current state and real address of the currently configured
3342 /* ncs_request() sub-function numbers */
3364 /* Real address of bytes to load or store bytes
3365 * into/out-of the MAU.
3378 unsigned long base; /* Real address base of queue */
3379 unsigned long end; /* Real address end of queue */
3395 * ARG0: NCS sub-function
3396 * ARG1: sub-function argument real address
3397 * ARG2: size in bytes of sub-function argument
3406 * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
3411 * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only
3416 * The real address of the sub-function argument must be aligned on at
3417 * least an 8-byte boundary.