Lines Matching +full:register +full:- +full:bit +full:- +full:led
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* fhc.h: FHC and Clock board register definitions.
10 /* Clock board register offsets. */
20 #define CLOCK_CTRL_LLED 0x04 /* Left LED, 0 == on */
21 #define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */
22 #define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */
24 /* Firehose controller register offsets */
30 #define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
39 #define FHC_PREGS_CTRL 0x20UL /* FHC Control Register */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
52 #define FHC_CONTROL_LLED 0x00000040 /* 0=Left LED ON */
53 #define FHC_CONTROL_MLED 0x00000020 /* 1=Middle LED ON */
54 #define FHC_CONTROL_RLED 0x00000010 /* 1=Right LED */
56 #define FHC_PREGS_BSR 0x30UL /* FHC Board Status Register */
57 #define FHC_BSR_DA64 0x00040000 /* Port A: 0=128bit 1=64bit data path */
58 #define FHC_BSR_DB64 0x00020000 /* Port B: 0=128bit 1=64bit data path */
64 #define FHC_BSR_NIA 0x0000001c /* Jumper, bit 18 in PROM space */
66 #define FHC_PREGS_ECC 0x40UL /* FHC ECC Control Register (16 bits) */
67 #define FHC_PREGS_JCTRL 0xf0UL /* FHC JTAG Control Register */
70 #define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */