Lines Matching +full:entry +full:- +full:address
5 * Copyright (C) 2003 - 2012 Paul Mundt
24 unsigned long address) in handle_tlbmiss() argument
31 pte_t entry; in handle_tlbmiss() local
36 * 29-bit mode, or due to PMB configuration in 32-bit mode. in handle_tlbmiss()
38 if (address >= P3SEG && address < P3_ADDR_MAX) { in handle_tlbmiss()
39 pgd = pgd_offset_k(address); in handle_tlbmiss()
41 if (unlikely(address >= TASK_SIZE || !current->mm)) in handle_tlbmiss()
44 pgd = pgd_offset(current->mm, address); in handle_tlbmiss()
47 p4d = p4d_offset(pgd, address); in handle_tlbmiss()
50 pud = pud_offset(p4d, address); in handle_tlbmiss()
53 pmd = pmd_offset(pud, address); in handle_tlbmiss()
56 pte = pte_offset_kernel(pmd, address); in handle_tlbmiss()
57 entry = *pte; in handle_tlbmiss()
58 if (unlikely(pte_none(entry) || pte_not_present(entry))) in handle_tlbmiss()
60 if (unlikely(error_code && !pte_write(entry))) in handle_tlbmiss()
64 entry = pte_mkdirty(entry); in handle_tlbmiss()
65 entry = pte_mkyoung(entry); in handle_tlbmiss()
67 set_pte(pte, entry); in handle_tlbmiss()
71 * SH-4 does not set MMUCR.RC to the corresponding TLB entry in in handle_tlbmiss()
73 * flush it in order to avoid potential TLB entry duplication. in handle_tlbmiss()
76 local_flush_tlb_one(get_asid(), address & PAGE_MASK); in handle_tlbmiss()
80 update_mmu_cache(NULL, address, pte); in handle_tlbmiss()