Lines Matching +full:sh +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0
15 #include <cpu/dma-register.h>
30 .name = "sh-sci",
51 .name = "sh-sci",
72 .name = "sh-tmu",
93 .name = "sh-tmu",
105 .end = 0xffe80000 + 0x58 - 1,
116 .name = "sh-rtc",
117 .id = -1,
209 * vectors are 0x640-0x6a0, 0x780-0x7a0
229 * vectors are 0x7c0-0x7e0, 0xd80-0xde0
239 .name = "sh-dma-engine",
249 .name = "sh-dma-engine",
304 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
315 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
316 INTC_VECT(RTC, 0x4c0),
360 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
366 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
409 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
443 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
446 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
458 /* disable IRQ7-0 */ in plat_irq_setup()
461 /* disable IRL3-0 + IRL7-4 */ in plat_irq_setup()
465 /* select IRL mode for IRL3-0 + IRL7-4 */ in plat_irq_setup()
468 /* disable holding function, ie enable "SH-4 Mode" */ in plat_irq_setup()
478 /* select IRQ mode for IRL3-0 + IRL7-4 */ in plat_irq_setup_pins()
483 /* enable IRL7-4 but don't provide any masking */ in plat_irq_setup_pins()
488 /* enable IRL0-3 but don't provide any masking */ in plat_irq_setup_pins()
493 /* enable IRL7-4 and mask using cpu intc controller */ in plat_irq_setup_pins()
498 /* enable IRL0-3 and mask using cpu intc controller */ in plat_irq_setup_pins()