Lines Matching +full:resource +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2006 - 2008 Paul Mundt
21 static struct resource scif0_resources[] = {
27 .name = "sh-sci",
28 .id = 0,
29 .resource = scif0_resources,
41 static struct resource scif1_resources[] = {
47 .name = "sh-sci",
48 .id = 1,
49 .resource = scif1_resources,
61 static struct resource scif2_resources[] = {
67 .name = "sh-sci",
68 .id = 2,
69 .resource = scif2_resources,
81 static struct resource scif3_resources[] = {
87 .name = "sh-sci",
88 .id = 3,
89 .resource = scif3_resources,
101 static struct resource scif4_resources[] = {
107 .name = "sh-sci",
108 .id = 4,
109 .resource = scif4_resources,
121 static struct resource scif5_resources[] = {
127 .name = "sh-sci",
128 .id = 5,
129 .resource = scif5_resources,
141 static struct resource scif6_resources[] = {
147 .name = "sh-sci",
148 .id = 6,
149 .resource = scif6_resources,
161 static struct resource scif7_resources[] = {
167 .name = "sh-sci",
168 .id = 7,
169 .resource = scif7_resources,
181 static struct resource scif8_resources[] = {
187 .name = "sh-sci",
188 .id = 8,
189 .resource = scif8_resources,
201 static struct resource scif9_resources[] = {
207 .name = "sh-sci",
208 .id = 9,
209 .resource = scif9_resources,
220 static struct resource tmu0_resources[] = {
228 .name = "sh-tmu",
229 .id = 0,
233 .resource = tmu0_resources,
241 static struct resource tmu1_resources[] = {
249 .name = "sh-tmu",
250 .id = 1,
254 .resource = tmu1_resources,
262 static struct resource tmu2_resources[] = {
270 .name = "sh-tmu",
271 .id = 2,
275 .resource = tmu2_resources,
476 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
509 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
512 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
524 /* disable IRQ7-0 */ in plat_irq_setup()
527 /* disable IRL3-0 + IRL7-4 */ in plat_irq_setup()
531 /* select IRL mode for IRL3-0 + IRL7-4 */ in plat_irq_setup()
534 /* disable holding function, ie enable "SH-4 Mode" */ in plat_irq_setup()
544 /* select IRQ mode for IRL3-0 + IRL7-4 */ in plat_irq_setup_pins()
549 /* enable IRL7-4 but don't provide any masking */ in plat_irq_setup_pins()
554 /* enable IRL0-3 but don't provide any masking */ in plat_irq_setup_pins()
559 /* enable IRL7-4 and mask using cpu intc controller */ in plat_irq_setup_pins()
564 /* enable IRL0-3 and mask using cpu intc controller */ in plat_irq_setup_pins()