Lines Matching +full:0 +full:x1a20
33 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
34 DEFINE_RES_IRQ(evt2irq(0x700)),
39 .id = 0,
53 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
54 DEFINE_RES_IRQ(evt2irq(0xb80)),
73 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
74 DEFINE_RES_IRQ(evt2irq(0xf00)),
92 DEFINE_RES_MEM(0xfe430000, 0x20),
93 DEFINE_RES_IRQ(evt2irq(0x580)),
94 DEFINE_RES_IRQ(evt2irq(0x5a0)),
99 .id = 0,
108 [0] = {
109 .start = 0xfe002000,
110 .end = 0xfe0020ff,
114 .start = evt2irq(0xcc0),
123 .addr = 0x1fe50030,
124 .chcr = SM_INC | RS_ERS | 0x40000000 |
126 .mid_rid = 0xc5,
130 .addr = 0x1fe50030,
131 .chcr = DM_INC | RS_ERS | 0x40000000 |
133 .mid_rid = 0xc6,
137 .addr = 0x1fcb0034,
138 .chcr = SM_INC | RS_ERS | 0x40000000 |
140 .mid_rid = 0xd3,
144 .addr = 0x1fcb0034,
145 .chcr = DM_INC | RS_ERS | 0x40000000 |
147 .mid_rid = 0xd7,
154 .addr = 0x1f4b000c,
155 .chcr = SM_INC | RS_ERS | 0x40000000 |
157 .mid_rid = 0x21,
161 .addr = 0x1f4b0014,
162 .chcr = DM_INC | RS_ERS | 0x40000000 |
164 .mid_rid = 0x22,
168 .addr = 0x1f4c000c,
169 .chcr = SM_INC | RS_ERS | 0x40000000 |
171 .mid_rid = 0x29,
175 .addr = 0x1f4c0014,
176 .chcr = DM_INC | RS_ERS | 0x40000000 |
178 .mid_rid = 0x2a,
182 .addr = 0x1f4d000c,
183 .chcr = SM_INC | RS_ERS | 0x40000000 |
185 .mid_rid = 0x41,
189 .addr = 0x1f4d0014,
190 .chcr = DM_INC | RS_ERS | 0x40000000 |
192 .mid_rid = 0x42,
196 .addr = 0xfe480004,
197 .chcr = SM_INC | RS_ERS | 0x40000000 |
199 .mid_rid = 0xc1,
203 .addr = 0xfe480004,
204 .chcr = DM_INC | RS_ERS | 0x40000000 |
206 .mid_rid = 0xc2,
213 .addr = 0x1e500012,
214 .chcr = SM_INC | RS_ERS | 0x40000000 |
216 .mid_rid = 0x21,
220 .addr = 0x1e500013,
221 .chcr = DM_INC | RS_ERS | 0x40000000 |
223 .mid_rid = 0x22,
227 .addr = 0x1e510012,
228 .chcr = SM_INC | RS_ERS | 0x40000000 |
230 .mid_rid = 0x29,
234 .addr = 0x1e510013,
235 .chcr = DM_INC | RS_ERS | 0x40000000 |
237 .mid_rid = 0x2a,
241 .addr = 0x1e520012,
242 .chcr = SM_INC | RS_ERS | 0x40000000 |
244 .mid_rid = 0xa1,
248 .addr = 0x1e520013,
249 .chcr = DM_INC | RS_ERS | 0x40000000 |
251 .mid_rid = 0xa2,
255 .addr = 0x1e530012,
256 .chcr = SM_INC | RS_ERS | 0x40000000 |
258 .mid_rid = 0xa9,
262 .addr = 0x1e530013,
263 .chcr = DM_INC | RS_ERS | 0x40000000 |
265 .mid_rid = 0xaf,
269 .addr = 0x1e540012,
270 .chcr = SM_INC | RS_ERS | 0x40000000 |
272 .mid_rid = 0xc5,
276 .addr = 0x1e540013,
277 .chcr = DM_INC | RS_ERS | 0x40000000 |
279 .mid_rid = 0xc6,
286 .addr = 0x1e550012,
287 .chcr = SM_INC | RS_ERS | 0x40000000 |
289 .mid_rid = 0x21,
293 .addr = 0x1e550013,
294 .chcr = DM_INC | RS_ERS | 0x40000000 |
296 .mid_rid = 0x22,
300 .addr = 0x1e560012,
301 .chcr = SM_INC | RS_ERS | 0x40000000 |
303 .mid_rid = 0x29,
307 .addr = 0x1e560013,
308 .chcr = DM_INC | RS_ERS | 0x40000000 |
310 .mid_rid = 0x2a,
314 .addr = 0x1e570012,
315 .chcr = SM_INC | RS_ERS | 0x40000000 |
317 .mid_rid = 0x41,
321 .addr = 0x1e570013,
322 .chcr = DM_INC | RS_ERS | 0x40000000 |
324 .mid_rid = 0x42,
328 .addr = 0x1e580012,
329 .chcr = SM_INC | RS_ERS | 0x40000000 |
331 .mid_rid = 0x45,
335 .addr = 0x1e580013,
336 .chcr = DM_INC | RS_ERS | 0x40000000 |
338 .mid_rid = 0x46,
342 .addr = 0x1e590012,
343 .chcr = SM_INC | RS_ERS | 0x40000000 |
345 .mid_rid = 0x51,
349 .addr = 0x1e590013,
350 .chcr = DM_INC | RS_ERS | 0x40000000 |
352 .mid_rid = 0x52,
358 .offset = 0,
359 .dmars = 0,
360 .dmars_bit = 0,
362 .offset = 0x10,
363 .dmars = 0,
366 .offset = 0x20,
368 .dmars_bit = 0,
370 .offset = 0x30,
374 .offset = 0x50,
376 .dmars_bit = 0,
378 .offset = 0x60,
442 /* channel 0 to 5 */
444 [0] = {
446 .start = 0xff608020,
447 .end = 0xff60808f,
452 .start = 0xff609000,
453 .end = 0xff60900b,
458 .start = evt2irq(0x640),
459 .end = evt2irq(0x640),
466 [0] = {
468 .start = 0xff618020,
469 .end = 0xff61808f,
474 .start = 0xff619000,
475 .end = 0xff61900b,
480 .start = evt2irq(0x640),
481 .end = evt2irq(0x640),
486 .start = evt2irq(0x7c0),
487 .end = evt2irq(0x7c0),
492 .start = evt2irq(0x7c0),
493 .end = evt2irq(0x7c0),
498 .start = evt2irq(0xd00),
499 .end = evt2irq(0xd00),
504 .start = evt2irq(0xd00),
505 .end = evt2irq(0xd00),
510 .start = evt2irq(0xd00),
511 .end = evt2irq(0xd00),
516 .start = evt2irq(0xd00),
517 .end = evt2irq(0xd00),
522 .start = evt2irq(0xd00),
523 .end = evt2irq(0xd00),
528 .start = evt2irq(0xd00),
529 .end = evt2irq(0xd00),
536 [0] = {
538 .start = 0xff708020,
539 .end = 0xff70808f,
544 .start = 0xff709000,
545 .end = 0xff70900b,
550 .start = evt2irq(0x2a60),
551 .end = evt2irq(0x2a60),
556 .start = evt2irq(0x2400),
557 .end = evt2irq(0x2480),
562 .start = evt2irq(0x24e0),
563 .end = evt2irq(0x24e0),
570 [0] = {
572 .start = 0xff718020,
573 .end = 0xff71808f,
578 .start = 0xff719000,
579 .end = 0xff71900b,
584 .start = evt2irq(0x2a80),
585 .end = evt2irq(0x2a80),
590 .start = evt2irq(0x2500),
591 .end = evt2irq(0x2580),
596 .start = evt2irq(0x2600),
597 .end = evt2irq(0x2600),
604 .id = 0,
644 .id = 0,
647 .coherent_dma_mask = 0xffffffff,
655 .start = 0xffd8ee70,
656 .end = 0xffd8eeff,
660 .start = evt2irq(0x8c0),
674 .start = 0xfe480000,
675 .end = 0xfe4800ff,
679 .start = evt2irq(0x1d80),
692 [0] = {
693 .start = 0xfe4f1000,
694 .end = 0xfe4f10ff,
698 .start = evt2irq(0x920),
699 .end = evt2irq(0x920),
716 [0] = {
717 .start = 0xfe4f1800,
718 .end = 0xfe4f18ff,
722 .start = evt2irq(0x920),
723 .end = evt2irq(0x920),
779 UNUSED = 0,
845 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
846 INTC_VECT(SDHI, 0x4c0),
847 INTC_VECT(DVC, 0x4e0),
848 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
849 INTC_VECT(IRQ10, 0x540),
850 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
851 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
852 INTC_VECT(HUDI, 0x600),
853 INTC_VECT(ARC4, 0x620),
854 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
855 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
856 INTC_VECT(DMAC0_5, 0x6c0),
857 INTC_VECT(IRQ11, 0x6e0),
858 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
859 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
860 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
861 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
862 INTC_VECT(USB0, 0x840),
863 INTC_VECT(IRQ12, 0x880),
864 INTC_VECT(JMC, 0x8a0),
865 INTC_VECT(SPI1, 0x8c0),
866 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
867 INTC_VECT(USB1, 0x920),
868 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
869 INTC_VECT(TMR45, 0xa40),
870 INTC_VECT(FRT, 0xa80),
871 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
872 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
873 INTC_VECT(LPC, 0xb20),
874 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
875 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
876 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
877 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
878 INTC_VECT(PECI2, 0xc40),
879 INTC_VECT(IRQ15, 0xc60),
880 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
881 INTC_VECT(SPI0, 0xcc0),
882 INTC_VECT(ADC1, 0xce0),
883 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
884 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
885 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
886 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
887 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
888 INTC_VECT(TMU5, 0xe40),
889 INTC_VECT(ADC0, 0xe60),
890 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
891 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
892 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
893 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
894 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
895 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
896 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
897 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
898 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
899 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
900 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
901 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
902 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
903 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
904 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
905 INTC_VECT(IIC6_2, 0x1920),
906 INTC_VECT(ONFICTL, 0x1960),
907 INTC_VECT(IIC6_3, 0x1980),
908 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
909 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
910 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
911 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
912 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
913 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
914 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
915 INTC_VECT(ECCU, 0x1cc0),
916 INTC_VECT(PCIC, 0x1ce0),
917 INTC_VECT(G200, 0x1d00),
918 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
919 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
920 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
921 INTC_VECT(PECI5, 0x1f00),
922 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
923 INTC_VECT(SGPIO, 0x1fc0),
924 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
925 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
926 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
927 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
928 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
929 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
930 INTC_VECT(DDRECC, 0x2620),
931 INTC_VECT(TSIP, 0x2640),
932 INTC_VECT(PCIE_BRIDGE, 0x27c0),
933 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
934 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
935 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
936 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
937 INTC_VECT(WDT8B, 0x2900),
938 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
939 INTC_VECT(GETHER2, 0x29a0),
940 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
941 INTC_VECT(PBIC, 0x2a40),
942 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
943 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
944 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
945 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
954 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
957 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
961 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
965 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
967 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
968 { 0, 0, 0, 0, 0, 0, 0, 0,
969 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
970 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
971 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
974 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
976 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
977 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
978 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
981 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
982 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
983 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
985 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
988 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
990 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
991 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
992 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
995 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
996 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
997 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
999 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
1002 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
1003 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
1004 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
1005 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
1006 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
1010 #define INTPRI 0xffd00010
1011 #define INT2PRI0 0xffd40000
1012 #define INT2PRI1 0xffd40004
1013 #define INT2PRI2 0xffd40008
1014 #define INT2PRI3 0xffd4000c
1015 #define INT2PRI4 0xffd40010
1016 #define INT2PRI5 0xffd40014
1017 #define INT2PRI6 0xffd40018
1018 #define INT2PRI7 0xffd4001c
1019 #define INT2PRI8 0xffd400a0
1020 #define INT2PRI9 0xffd400a4
1021 #define INT2PRI10 0xffd400a8
1022 #define INT2PRI11 0xffd400ac
1023 #define INT2PRI12 0xffd400b0
1024 #define INT2PRI13 0xffd400b4
1025 #define INT2PRI14 0xffd400b8
1026 #define INT2PRI15 0xffd400bc
1027 #define INT2PRI16 0xffd10000
1028 #define INT2PRI17 0xffd10004
1029 #define INT2PRI18 0xffd10008
1030 #define INT2PRI19 0xffd1000c
1031 #define INT2PRI20 0xffd10010
1032 #define INT2PRI21 0xffd10014
1033 #define INT2PRI22 0xffd10018
1034 #define INT2PRI23 0xffd1001c
1035 #define INT2PRI24 0xffd100a0
1036 #define INT2PRI25 0xffd100a4
1037 #define INT2PRI26 0xffd100a8
1038 #define INT2PRI27 0xffd100ac
1039 #define INT2PRI28 0xffd100b0
1040 #define INT2PRI29 0xffd100b4
1041 #define INT2PRI30 0xffd100b8
1042 #define INT2PRI31 0xffd100bc
1043 #define INT2PRI32 0xffd20000
1044 #define INT2PRI33 0xffd20004
1045 #define INT2PRI34 0xffd20008
1046 #define INT2PRI35 0xffd2000c
1047 #define INT2PRI36 0xffd20010
1048 #define INT2PRI37 0xffd20014
1049 #define INT2PRI38 0xffd20018
1050 #define INT2PRI39 0xffd2001c
1051 #define INT2PRI40 0xffd200a0
1052 #define INT2PRI41 0xffd200a4
1053 #define INT2PRI42 0xffd200a8
1054 #define INT2PRI43 0xffd200ac
1055 #define INT2PRI44 0xffd200b0
1056 #define INT2PRI45 0xffd200b4
1057 #define INT2PRI46 0xffd200b8
1058 #define INT2PRI47 0xffd200bc
1061 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
1064 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
1065 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
1066 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
1067 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
1068 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
1069 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
1070 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
1071 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
1072 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
1073 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
1074 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
1075 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
1076 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
1077 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
1079 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
1080 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
1081 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
1082 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
1083 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
1084 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
1085 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
1086 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
1087 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
1088 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
1089 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
1090 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
1091 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
1092 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
1093 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
1094 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
1095 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1096 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1097 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1098 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1099 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1100 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1101 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1102 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1103 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1104 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1105 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1106 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1107 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1108 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1109 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1110 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1114 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12,
1124 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
1125 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
1129 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
1130 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
1134 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
1139 { 0xffd00024, 0, 32, /* INTREQ */
1153 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
1154 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
1155 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
1156 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
1157 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
1158 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
1159 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
1160 INTC_VECT(IRL0_HHHL, 0x3c0),
1164 INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
1165 INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
1166 INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
1167 INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
1168 INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
1169 INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
1170 INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
1171 INTC_VECT(IRL4_HHHL, 0x3c0),
1180 #define INTC_ICR0 0xffd00000
1181 #define INTC_INTMSK0 0xffd00044
1182 #define INTC_INTMSK1 0xffd00048
1183 #define INTC_INTMSK2 0xffd40080
1184 #define INTC_INTMSKCLR1 0xffd00068
1185 #define INTC_INTMSKCLR2 0xffd40084
1189 /* disable IRQ3-0 + IRQ7-4 */ in plat_irq_setup()
1190 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
1192 /* disable IRL3-0 + IRL7-4 */ in plat_irq_setup()
1193 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
1194 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
1196 /* select IRL mode for IRL3-0 + IRL7-4 */ in plat_irq_setup()
1197 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); in plat_irq_setup()
1200 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); in plat_irq_setup()
1210 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); in plat_irq_setup_pins()
1214 /* select IRQ mode for IRL3-0 */ in plat_irq_setup_pins()
1215 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); in plat_irq_setup_pins()
1220 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
1221 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
1225 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
1226 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); in plat_irq_setup_pins()
1230 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
1235 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()