Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x03ffffff
1 /* SPDX-License-Identifier: GPL-2.0 */
7 * It can be changed with DIP switch(S2-5).
9 * phys address | S2-5 = OFF | S2-5 = ON
10 * -----------------------------+---------------+---------------
11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
24 #define NOR_FLASH_SIZE 0x04000000
26 #define PLD_BASE_ADDR 0x04000000
27 #define PLD_PCICR (PLD_BASE_ADDR + 0x00)
28 #define PLD_LCD_BK_CONTR (PLD_BASE_ADDR + 0x02)
29 #define PLD_LOCALCR (PLD_BASE_ADDR + 0x04)
30 #define PLD_POFCR (PLD_BASE_ADDR + 0x06)
31 #define PLD_LEDCR (PLD_BASE_ADDR + 0x08)
32 #define PLD_SWSR (PLD_BASE_ADDR + 0x0a)
33 #define PLD_VERSR (PLD_BASE_ADDR + 0x0c)
34 #define PLD_MMSR (PLD_BASE_ADDR + 0x0e)
36 #define PCA9564_ADDR 0x06000000 /* I2C */
37 #define PCA9564_SIZE 0x00000100
39 #define PCA9564_PROTO_32BIT_ADDR 0x14000000
41 #define SM107_MEM_ADDR 0x10000000
42 #define SM107_MEM_SIZE 0x00e00000
43 #define SM107_REG_ADDR 0x13e00000
44 #define SM107_REG_SIZE 0x00200000
47 #define R8A66597_ADDR 0x14000000 /* USB */
48 #define CG200_ADDR 0x18000000 /* SD */
50 #define R8A66597_ADDR 0x08000000
51 #define CG200_ADDR 0x0c000000
54 #define R8A66597_SIZE 0x00000100
55 #define CG200_SIZE 0x00010000