Lines Matching full:r
34 #define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */
43 #define SH4A_PCIEVCR1 (0x000004) /* R - 0x0000 0000 32*/
44 #define BITS_BADOPC (5) /* 5 BADOPC 0 R/W */
46 #define BITS_BADDEST (4) /*4 BADDEST 0 R/W */
48 #define BITS_UNSOLRESP (3) /* 3 UNSOLRESP 0 R/W */
56 #define SH4A_PCIEENBLR (0x000008) /* R/W - 0x0000 0001 32 */
59 #define SH4A_PCIEECR (0x00000C) /* R/W - 0x0000 0000 32 */
60 #define BITS_ENBL (0) /* 0 ENBL 0 R/W */
64 #define SH4A_PCIEPAR (0x000010) /* R/W - 0x0000 0000 32 */
77 #define SH4A_PCIEPCTLR (0x000018) /* R/W - 0x0000 0000 32 */
86 #define SH4A_PCIEPDR (0x000020) /* R/W - 0x0000 0000 32 */
91 #define SH4A_PCIEMSGALR (0x000030) /* R/W - 0x0000 0000 32 */
96 #define SH4A_PCIEMSGAHR (0x000034) /* R/W - 0x0000 0000 32 */
101 #define SH4A_PCIEMSGCTLR (0x000038) /* R/W - 0x0000 0000 32 */
117 #define SH4A_PCIEUNLOCKCR (0x000048) /* R/W - 0x0000 0000 32 */
120 #define SH4A_PCIEIDR (0x000060) /* R/W - 0x0101 1101 32 */
123 #define SH4A_PCIEDBGCTLR (0x000100) /* R/W - 0x0000 0000 32 */
126 #define SH4A_PCIEINTXR (0x004000) /* R/W - 0x0000 0000 32 */
129 #define SH4A_PCIERMSGR (0x004010) /* R/W - 0x0000 0000 32 */
132 #define SH4A_PCIERSTR(x) (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */
135 #define SH4A_PCIESRSTR (0x008040) /* R/W - 0x0000 0000 32 */
138 #define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */
143 #define SH4A_PCIERMSGIER (0x004040) /* R/W - 0x0000 0000 32 */
146 #define SH4A_PCIEPHYADRR (0x010004) /* R/W - 0x0000 0000 32 */
157 #define SH4A_PCIEPHYDINR (0x010008) /* R/W - 0x0000 0000 32 */
160 #define SH4A_PCIEPHYDOUTR (0x01000C) /* R/W - 0x0000 0000 32 */
163 #define SH4A_PCIEPHYSR (0x010010) /* R/W - 0x0000 0000 32 */ // Rev1.171 end.
166 #define SH4A_PCIEPHYDATAR (0x00008) /* R/W - 0xxxxx xxxx 32 */
171 #define SH4A_PCIETCTLR (0x020000) /* R/W R/W 0x0000 0000 32 */
176 #define SH4A_PCIETSTR (0x020004) /* R 0x0000 0000 32 */
179 #define SH4A_PCIEINTR (0x020008) /* R/W R/W 0x0000 0000 32 */
220 #define SH4A_PCIEINTER (0x02000C) /* R/W R/W 0x0000 0000 32 */
261 #define SH4A_PCIEEHR(x) (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */
264 #define SH4A_PCIEAIR (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */
267 #define SH4A_PCIECIR (SH4A_PCIE_BASE) /* R/W R/W 0xxxxx xxxx 32 */
270 #define SH4A_PCIEERRFR (0x020020) /* R/W R/W 0xxxxx xxxx 32 */ // Rev1.18
273 #define SH4A_PCIEERRFER (0x020024) /* R/W R/W 0x0000 0000 32 */
276 #define SH4A_PCIEERRFR2 (0x020028) /* R/W R/W 0x0000 0000 32 */
279 #define SH4A_PCIEMSIR (0x020040) /* R/W - 0x0000 0000 32 */
282 #define SH4A_PCIEMSIFR (0x020044) /* R/W R/W 0x0000 0000 32 */
285 #define SH4A_PCIEPWRCTLR (0x020100) /* R/W - 0x0000 0000 32 */
288 #define SH4A_PCIEPCCTLR (0x020180) /* R/W - 0x0000 0000 32 */
292 #define SH4A_PCIELAR0 (0x020200) /* R/W R/W 0x0000 0000 32 */
296 #define SH4A_PCIE_020204 (0x020204) /* R/W R/W 0x0000 0000 32 */
299 #define SH4A_PCIELAMR0 (0x020208) /* R/W R/W 0x0000 0000 32 */
306 #define SH4A_PCIECSCR0 (0x020210) /* R/W R/W 0x0000 0000 32 */
313 #define SH4A_PCIECSAR0 (0x020214) /* R/W R/W 0x0000 0000 32 */
318 #define SH4A_PCIESTCTLR0 (0x020218) /* R/W R/W 0x0000 0000 32 */
322 #define SH4A_PCIE_020224 (0x020224) /* R/W R/W 0x0000 0000 32 */
324 #define SH4A_PCIELAR1 (0x020220) /* R/W R/W 0x0000 0000 32 */
325 #define SH4A_PCIELAMR1 (0x020228) /* R/W R/W 0x0000 0000 32 */
326 #define SH4A_PCIECSCR1 (0x020230) /* R/W R/W 0x0000 0000 32 */
327 #define SH4A_PCIECSAR1 (0x020234) /* R/W R/W 0x0000 0000 32 */
328 #define SH4A_PCIESTCTLR1 (0x020238) /* R/W R/W 0x0000 0000 32 */
330 #define SH4A_PCIELAR2 (0x020240) /* R/W R/W 0x0000 0000 32 */
331 #define SH4A_PCIE_020244 (0x020244) /* R/W R/W 0x0000 0000 32 */
332 #define SH4A_PCIELAMR2 (0x020248) /* R/W R/W 0x0000 0000 32 */
333 #define SH4A_PCIECSCR2 (0x020250) /* R/W R/W 0x0000 0000 32 */
334 #define SH4A_PCIECSAR2 (0x020254) /* R/W R/W 0x0000 0000 32 */
335 #define SH4A_PCIESTCTLR2 (0x020258) /* R/W R/W 0x0000 0000 32 */
337 #define SH4A_PCIELAR3 (0x020260) /* R/W R/W 0x0000 0000 32 */
338 #define SH4A_PCIE_020264 (0x020264) /* R/W R/W 0x0000 0000 32 */
339 #define SH4A_PCIELAMR3 (0x020268) /* R/W R/W 0x0000 0000 32 */
340 #define SH4A_PCIECSCR3 (0x020270) /* R/W R/W 0x0000 0000 32 */
341 #define SH4A_PCIECSAR3 (0x020274) /* R/W R/W 0x0000 0000 32 */
342 #define SH4A_PCIESTCTLR3 (0x020278) /* R/W R/W 0x0000 0000 32 */
344 #define SH4A_PCIELAR4 (0x020280) /* R/W R/W 0x0000 0000 32 */
345 #define SH4A_PCIE_020284 (0x020284) /* R/W R/W 0x0000 0000 32 */
346 #define SH4A_PCIELAMR4 (0x020288) /* R/W R/W 0x0000 0000 32 */
347 #define SH4A_PCIECSCR4 (0x020290) /* R/W R/W 0x0000 0000 32 */
348 #define SH4A_PCIECSAR4 (0x020294) /* R/W R/W 0x0000 0000 32 */
349 #define SH4A_PCIESTCTLR4 (0x020298) /* R/W R/W 0x0000 0000 32 */
351 #define SH4A_PCIELAR5 (0x0202A0) /* R/W R/W 0x0000 0000 32 */
352 #define SH4A_PCIE_0202A4 (0x0202A4) /* R/W R/W 0x0000 0000 32 */
353 #define SH4A_PCIELAMR5 (0x0202A8) /* R/W R/W 0x0000 0000 32 */
354 #define SH4A_PCIECSCR5 (0x0202B0) /* R/W R/W 0x0000 0000 32 */
355 #define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */
356 #define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */
359 #define SH4A_PCIEPARL(x) (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
364 #define SH4A_PCIEPARH(x) (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
369 #define SH4A_PCIEPAMR(x) (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
386 #define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */
387 #define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */
388 #define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */
389 #define SH4A_PCIEDMDAR0 (0x021108) /* R/W R/W 0x0000 0000 32 */
390 #define SH4A_PCIEDMDAHR0 (0x02110C) /* R/W R/W 0x0000 0000 32 */
391 #define SH4A_PCIEDMBCNTR0 (0x021110) /* R/W R/W 0x0000 0000 32 */
392 #define SH4A_PCIEDMSBCNTR0 (0x021114) /* R/W R/W 0x0000 0000 32 */
393 #define SH4A_PCIEDMSTRR0 (0x021118) /* R/W R/W 0x0000 0000 32 */
394 #define SH4A_PCIEDMCCAR0 (0x02111C) /* R/W R/W 0x0000 0000 32 */
395 #define SH4A_PCIEDMCCR0 (0x021120) /* R/W R/W 0x0000 0000 32 */
396 #define SH4A_PCIEDMCC2R0 (0x021124) /* R/W R/W 0x0000 0000 - */
397 #define SH4A_PCIEDMCCCR0 (0x021128) /* R/W R/W 0x0000 0000 32 */
398 #define SH4A_PCIEDMCHSR0 (0x02112C) /* R/W - 0x0000 0000 32 */
399 #define SH4A_PCIEDMSAR1 (0x021140) /* R/W R/W 0x0000 0000 32 */
400 #define SH4A_PCIEDMSAHR1 (0x021144) /* R/W R/W 0x0000 0000 32 */
401 #define SH4A_PCIEDMDAR1 (0x021148) /* R/W R/W 0x0000 0000 32 */
402 #define SH4A_PCIEDMDAHR1 (0x02114C) /* R/W R/W 0x0000 0000 32 */
403 #define SH4A_PCIEDMBCNTR1 (0x021150) /* R/W R/W 0x0000 0000 32 */
404 #define SH4A_PCIEDMSBCNTR1 (0x021154) /* R/W R/W 0x0000 0000 32 */
405 #define SH4A_PCIEDMSTRR1 (0x021158) /* R/W R/W 0x0000 0000 32 */
406 #define SH4A_PCIEDMCCAR1 (0x02115C) /* R/W R/W 0x0000 0000 32 */
407 #define SH4A_PCIEDMCCR1 (0x021160) /* R/W R/W 0x0000 0000 32 */
408 #define SH4A_PCIEDMCC2R1 (0x021164) /* R/W R/W 0x0000 0000 - */
409 #define SH4A_PCIEDMCCCR1 (0x021168) /* R/W R/W 0x0000 0000 32 */
410 #define SH4A_PCIEDMCHSR1 (0x02116C) /* R/W - 0x0000 0000 32 */
411 #define SH4A_PCIEDMSAR2 (0x021180) /* R/W R/W 0x0000 0000 32 */
412 #define SH4A_PCIEDMSAHR2 (0x021184) /* R/W R/W 0x0000 0000 32 */
413 #define SH4A_PCIEDMDAR2 (0x021188) /* R/W R/W 0x0000 0000 32 */
414 #define SH4A_PCIEDMDAHR2 (0x02118C) /* R/W R/W 0x0000 0000 32 */
415 #define SH4A_PCIEDMBCNTR2 (0x021190) /* R/W R/W 0x0000 0000 32 */
416 #define SH4A_PCIEDMSBCNTR2 (0x021194) /* R/W R/W 0x0000 0000 32 */
417 #define SH4A_PCIEDMSTRR2 (0x021198) /* R/W R/W 0x0000 0000 32 */
418 #define SH4A_PCIEDMCCAR2 (0x02119C) /* R/W R/W 0x0000 0000 32 */
419 #define SH4A_PCIEDMCCR2 (0x0211A0) /* R/W R/W 0x0000 0000 32 */
420 #define SH4A_PCIEDMCC2R2 (0x0211A4) /* R/W R/W 0x0000 0000 - */
421 #define SH4A_PCIEDMCCCR2 (0x0211A8) /* R/W R/W 0x0000 0000 32 */
422 #define SH4A_PCIEDMSAR3 (0x0211C0) /* R/W R/W 0x0000 0000 32 */
423 #define SH4A_PCIEDMSAHR3 (0x0211C4) /* R/W R/W 0x0000 0000 32 */
424 #define SH4A_PCIEDMDAR3 (0x0211C8) /* R/W R/W 0x0000 0000 32 */
425 #define SH4A_PCIEDMDAHR3 (0x0211CC) /* R/W R/W 0x0000 0000 32 */
426 #define SH4A_PCIEDMBCNTR3 (0x0211D0) /* R/W R/W 0x0000 0000 32 */
427 #define SH4A_PCIEDMSBCNTR3 (0x0211D4) /* R/W R/W 0x0000 0000 32 */
428 #define SH4A_PCIEDMSTRR3 (0x0211D8) /* R/W R/W 0x0000 0000 32 */
429 #define SH4A_PCIEDMCCAR3 (0x0211DC) /* R/W R/W 0x0000 0000 32 */
430 #define SH4A_PCIEDMCCR3 (0x0211E0) /* R/W R/W 0x0000 0000 32 */
431 #define SH4A_PCIEDMCC2R3 (0x0211E4) /* R/W R/W 0x0000 0000 - */
432 #define SH4A_PCIEDMCCCR3 (0x0211E8) /* R/W R/W 0x0000 0000 32 */
433 #define SH4A_PCIEDMCHSR3 (0x0211EC) /* R/W R/W 0x0000 0000 32 */
434 #define SH4A_PCIEPCICONF0 (0x040000) /* R R - 8/16/32 */
435 #define SH4A_PCIEPCICONF1 (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */
436 #define SH4A_PCIEPCICONF2 (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */
437 #define SH4A_PCIEPCICONF3 (0x04000C) /* R/W R/W 0x0000 0000 8/16/32 */
438 #define SH4A_PCIEPCICONF4 (0x040010) /* - R/W - 8/16/32 */
439 #define SH4A_PCIEPCICONF5 (0x040014) /* - R/W - 8/16/32 */
440 #define SH4A_PCIEPCICONF6 (0x040018) /* - R/W - 8/16/32 */
441 #define SH4A_PCIEPCICONF7 (0x04001C) /* - R/W - 8/16/32 */
442 #define SH4A_PCIEPCICONF8 (0x040020) /* - R/W - 8/16/32 */
443 #define SH4A_PCIEPCICONF9 (0x040024) /* - R/W - 8/16/32 */
444 #define SH4A_PCIEPCICONF10 (0x040028) /* R/W R/W 0x0000 0000 8/16/32 */
445 #define SH4A_PCIEPCICONF11 (0x04002C) /* R/W R/W 0x0000 0000 8/16/32 */
446 #define SH4A_PCIEPCICONF12 (0x040030) /* R/W R/W 0x0000 0000 8/16/32 */
447 #define SH4A_PCIEPCICONF13 (0x040034) /* R/W R/W 0x0000 0040 8/16/32 */
448 #define SH4A_PCIEPCICONF14 (0x040038) /* R/W R/W 0x0000 0000 8/16/32 */
449 #define SH4A_PCIEPCICONF15 (0x04003C) /* R/W R/W 0x0000 00FF 8/16/32 */
450 #define SH4A_PCIEPMCAP0 (0x040040) /* R/W R 0x0003 5001 8/16/32 */
451 #define SH4A_PCIEPMCAP1 (0x040044) /* R/W R/W 0x0000 0000 8/16/32 */
452 #define SH4A_PCIEMSICAP0 (0x040050) /* R/W R/W 0x0180 7005 8/16/32 */
453 #define SH4A_PCIEMSICAP1 (0x040054) /* R/W R/W 0x0000 0000 8/16/32 */
454 #define SH4A_PCIEMSICAP2 (0x040058) /* R/W R/W 0x0000 0000 8/16/32 */
455 #define SH4A_PCIEMSICAP3 (0x04005C) /* R/W R/W 0x0000 0000 8/16/32 */
456 #define SH4A_PCIEMSICAP4 (0x040060) /* R/W R/W 0x0000 0000 8/16/32 */
457 #define SH4A_PCIEMSICAP5 (0x040064) /* R/W R/W 0x0000 0000 8/16/32 */
458 #define SH4A_PCIEEXPCAP0 (0x040070) /* R/W R/W 0x0001 0010 8/16/32 */
459 #define SH4A_PCIEEXPCAP1 (0x040074) /* R/W R 0x0000 0005 8/16/32 */
460 #define SH4A_PCIEEXPCAP2 (0x040078) /* R/W R/W 0x0000 0801 8/16/32 */
461 #define SH4A_PCIEEXPCAP3 (0x04007C) /* R/W R 0x0003 F421 8/16/32 */
462 #define SH4A_PCIEEXPCAP4 (0x040080) /* R/W R/W 0x0041 0000 8/16/32 */
463 #define SH4A_PCIEEXPCAP5 (0x040084) /* R/W R/W 0x0000 0000 8/16/32 */
464 #define SH4A_PCIEEXPCAP6 (0x040088) /* R/W R/W 0x0000 03C0 8/16/32 */
465 #define SH4A_PCIEEXPCAP7 (0x04008C) /* R/W R/W 0x0000 0000 8/16/32 */
466 #define SH4A_PCIEEXPCAP8 (0x040090) /* R/W R/W 0x0000 0000 8/16/32 */
467 #define SH4A_PCIEVCCAP0 (0x040100) /* R/W R 0x1B01 0002 8/16/32 */
468 #define SH4A_PCIEVCCAP1 (0x040104) /* R R 0x0000 0001 8/16/32 */
469 #define SH4A_PCIEVCCAP2 (0x040108) /* R R 0x0000 0000 8/16/32 */
470 #define SH4A_PCIEVCCAP3 (0x04010C) /* R R/W 0x0000 0000 8/16/32 */
471 #define SH4A_PCIEVCCAP4 (0x040110) /* R/W R/W 0x0000 0000 8/16/32 */
472 #define SH4A_PCIEVCCAP5 (0x040114) /* R/W R/W 0x8000 00FF 8/16/32 */
473 #define SH4A_PCIEVCCAP6 (0x040118) /* R/W R 0x0002 0000 8/16/32 */
474 #define SH4A_PCIEVCCAP7 (0x04011C) /* R/W R/W 0x0000 0000 8/16/32 */
475 #define SH4A_PCIEVCCAP8 (0x040120) /* R/W R/W 0x0000 0000 8/16/32 */
476 #define SH4A_PCIEVCCAP9 (0x040124) /* R/W R 0x0002 0000 8/16/32 */
477 #define SH4A_PCIENUMCAP0 (0x0001B0) /* RW R 0x0001 0003 8/16/32 */
478 #define SH4A_PCIENUMCAP1 (0x0001B4) /* R R 0x0000 0000 8/16/32 */
479 #define SH4A_PCIENUMCAP2 (0x0001B8) /* R R 0x0000 0000 8/16/32 */
480 #define SH4A_PCIEIDSETR0 (0x041000) /* R/W R 0x0000 FFFF 16/32 */
481 #define SH4A_PCIEIDSETR1 (0x041004) /* R/W R 0xFF00 0000 16/32 */
482 #define SH4A_PCIEBAR0SETR (0x041008) /* R/W R 0x0000 0000 16/32 */
483 #define SH4A_PCIEBAR1SETR (0x04100C) /* R/W R 0x0000 0000 16/32 */
484 #define SH4A_PCIEBAR2SETR (0x041010) /* R/W R 0x0000 0000 16/32 */
485 #define SH4A_PCIEBAR3SETR (0x041014) /* R/W R 0x0000 0000 16/32 */
486 #define SH4A_PCIEBAR4SETR (0x041018) /* R/W R 0x0000 0000 16/32 */
487 #define SH4A_PCIEBAR5SETR (0x04101C) /* R/W R 0x0000 0000 16/32 */
488 #define SH4A_PCIECISSETR (0x041020) /* R/W R 0x0000 0000 16/32 */
489 #define SH4A_PCIEIDSETR2 (0x041024) /* R/W R 0x0000 0000 16/32 */
490 #define SH4A_PCIEEROMSETR (0x041028) /* R/W R 0x0000 0000 16/32 */
491 #define SH4A_PCIEDSERSETR0 (0x04102C) /* R/W R 0x0000 0000 16/32 */
492 #define SH4A_PCIEDSERSETR1 (0x041030) /* R/W R 0x0000 0000 16/32 */
493 #define SH4A_PCIECTLR (0x041040) /* R/W R 0x0000 0000 16/32 */
494 #define SH4A_PCIETLSR (0x041044) /* R/W1C R 0x0000 0000 16/32 */
495 #define SH4A_PCIETLCTLR (0x041048) /* R/W R 0x0000 0000 16/32 */
496 #define SH4A_PCIEDLSR (0x04104C) /* R/W1C R 0x4003 0000 16/32 */
497 #define SH4A_PCIEDLCTLR (0x041050) /* R R 0x0000 0000 16/32 */
498 #define SH4A_PCIEMACSR (0x041054) /* R/W1C R 0x0041 0000 16/32 */
499 #define SH4A_PCIEMACCTLR (0x041058) /* R/W R 0x0000 0000 16/32 */
501 #define SH4A_PCIEPMSTR (0x04105C) /* R/W1C R 0x0000 0000 16/32 */
502 #define SH4A_PCIEPMCTLR (0x041060) /* R/W R 0x0000 0000 16/32 */
503 #define SH4A_PCIETLINTENR (0x041064) /* R/W R 0x0000 0000 16/32 */
504 #define SH4A_PCIEDLINTENR (0x041068) /* R/W R 0x0000 0000 16/32 */
506 #define SH4A_PCIEMACINTENR (0x04106C) /* R/W R 0x0000 0000 16/32 */
507 #define SH4A_PCIEPMINTENR (0x041070) /* R/W R 0x0000 0000 16/32 */
508 #define SH4A_PCIETXDCTLR (0x044000) /* R/W - H'00000000_00000000 32/64 */
509 #define SH4A_PCIETXCTLR (0x044020) /* R/W - H'00000000_00000000 32/64 */
510 #define SH4A_PCIETXSR (0x044028) /* R - H'00000000_00000000 32/64 */
511 #define SH4A_PCIETXVC0DCTLR (0x044100) /* R/W - H'00000000_00000000 32/64 */
512 #define SH4A_PCIETXVC0SR (0x044108) /* R/W - H'00888000_00000000 32/64 */
519 #define SH4A_PCIETXVCXDCTLR (0x044200) /* R/W - H'00000000_00000000 32/64 */
520 #define SH4A_PCIETXVCXSR (0x044208) /* R/W - H'00000000_00000000 32/64 */
529 #define SH4A_PCIEERPHR (0x046010) /* R - H'00000000_00000000 32/64 */
530 #define SH4A_PCIEERPERR (0x046018) /* R - H'00000000_00000000 32/64 */
533 #define SH4A_PCIEVC0PDRXR (0x046140) /* R - H'00000000_00000000 32/64 */
534 #define SH4A_PCIEVC0PHRXR (0x046148) /* R - H'00000000_00000000 32/64 */
535 #define SH4A_PCIEVC0PERR (0x046150) /* R - H'00000000_00000000 32/64 */
536 #define SH4A_PCIEVC0NPDRXR (0x046158) /* R - H'00000000_00000000 32/64 */
537 #define SH4A_PCIEVC0NPHRXR (0x046160) /* R - H'00000000_00000000 32/64 */
538 #define SH4A_PCIEVC0NPERR (0x046168) /* R - H'00000000_00000000 32/64 */
539 #define SH4A_PCIEVC0CDRXR (0x046170) /* R - H'00000000_00000000 32/64 */
540 #define SH4A_PCIEVC0CHRXR (0x046178) /* R - H'00000000_00000000 32/64 */
541 #define SH4A_PCIEVC0CERR (0x046180) /* R - H'00000000_00000000 32/64 */
544 #define SH4A_PCIEVCXPDRXR (0x046240) /* R - H'00000000_00000000 32/64 */
545 #define SH4A_PCIEVCXPHRXR (0x046248) /* R H'00000000_00000000 32/64 */
546 #define SH4A_PCIEVCXPERR (0x046250) /* R H'00000000_00000000 32/64 */
547 #define SH4A_PCIEVCXNPDRXR (0x046258) /* R H'00000000_00000000 32/64 */
548 #define SH4A_PCIEVCXNPHRXR (0x046260) /* R H'00000000_00000000 32/64 */
549 #define SH4A_PCIEVCXNPERR (0x046268) /* R H'00000000_00000000 32/64 */
550 #define SH4A_PCIEVCXCDRXR (0x046270) /* R H'00000000_00000000 32/64 */
551 #define SH4A_PCIEVCXCHRXR (0x046278) /* R H'00000000_00000000 32/64 */
552 #define SH4A_PCIEVCXCERR (0x046280) /* R H'00000000_00000000 32/64 */