Lines Matching +full:alternative +full:- +full:a
1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Derived from "include/asm-i386/spinlock.h"
17 #include <asm/alternative.h>
27 ALTERNATIVE(" ly %[lockval],%[offzero](%%r0)\n", in spinlock_lockval()
33 "m" (((struct lowcore *)0)->spinlock_lockval)); in spinlock_lockval()
47 * We make no fairness assumptions. They have a cost.
71 return READ_ONCE(lp->lock) != 0; in arch_spin_is_locked()
79 return likely(arch_try_cmpxchg(&lp->lock, &old, spinlock_lockval())); in arch_spin_trylock_once()
97 typecheck(int, lp->lock); in arch_spin_unlock()
100 ALTERNATIVE("nop", ".insn rre,0xb2fa0000,7,0", ALT_FACILITY(49)) /* NIAI 7 */ in arch_spin_unlock()
102 : [lock] "=Q" (((unsigned short *)&lp->lock)[1]) in arch_spin_unlock()
108 * Read-write spinlocks, allowing multiple readers
113 * can "mix" irq-safe locks - any writer needs to get a
114 * irq-safe write-lock, but readers can get non-irqsafe
115 * read-locks.
128 old = __atomic_add(1, &rw->cnts); in arch_read_lock()
135 __atomic_add_const_barrier(-1, &rw->cnts); in arch_read_unlock()
142 if (!arch_try_cmpxchg(&rw->cnts, &old, 0x30000)) in arch_write_lock()
148 __atomic_add_barrier(-0x30000, &rw->cnts); in arch_write_unlock()
156 old = READ_ONCE(rw->cnts); in arch_read_trylock()
157 return (!(old & 0xffff0000) && arch_try_cmpxchg(&rw->cnts, &old, old + 1)); in arch_read_trylock()
164 old = READ_ONCE(rw->cnts); in arch_write_trylock()
165 return !old && arch_try_cmpxchg(&rw->cnts, &old, 0x30000); in arch_write_trylock()