120 struct zpci_dev {  struct
122 	struct list_head entry;		/* list of all zpci_devices, needed for hotplug, etc. */  argument
123 	struct list_head iommu_list;
124 	struct kref kref;
125 	struct rcu_head rcu;
126 	struct hotplug_slot hotplug_slot;
128 	struct mutex state_lock;	/* protect state changes */
129 	enum zpci_state state;
130 	u32		fid;		/* function ID, used by sclp */
131 	u32		fh;		/* function handle, used by insn's */
132 	u32		gisa;		/* GISA designation for passthrough */
133 	u16		vfn;		/* virtual function number */
134 	u16		pchid;		/* physical channel ID */
135 	u16		maxstbl;	/* Maximum store block size */
136 	u16		rid;		/* RID as supplied by firmware */
137 	u16		tid;		/* Topology for which RID is valid */
138 	u8		pfgid;		/* function group ID */
139 	u8		pft;		/* pci function type */
140 	u8		port;
141 	u8		fidparm;
142 	u8		dtsm;		/* Supported DT mask */
143 	u8		rid_available	: 1;
144 	u8		has_hp_slot	: 1;
145 	u8		has_resources	: 1;
146 	u8		is_physfn	: 1;
147 	u8		util_str_avail	: 1;
148 	u8		tid_avail	: 1;
149 	u8		rtr_avail	: 1; /* Relaxed translation allowed */
150 	unsigned int	devfn;		/* DEVFN part of the RID*/
152 	u8 pfip[CLP_PFIP_NR_SEGMENTS];	/* pci function internal path */
153 	u32 uid;			/* user defined id */
154 	u8 util_str[CLP_UTIL_STR_LEN];	/* utility string */
157 	u64		msi_addr;	/* MSI address */
158 	unsigned int	max_msi;	/* maximum number of MSI's */
159 	unsigned int	msi_first_bit;
160 	unsigned int	msi_nr_irqs;
161 	struct airq_iv *aibv;		/* adapter interrupt bit vector */
162 	unsigned long	aisb;		/* number of the summary bit */
165 	unsigned long	*dma_table;
166 	int		tlb_refresh;
168 	struct iommu_device iommu_dev;  /* IOMMU core handle */
170 	char res_name[16];
171 	bool mio_capable;
172 	struct zpci_bar_struct bars[PCI_STD_NUM_BARS];
196 static inline bool zdev_enabled(struct zpci_dev *zdev)  in zdev_enabled()  argument