Lines Matching full:v1

97 	.ifc \vxr,%v1
198  * @v1:		Vector register designated operand whose MSB is stored in
211  * Note: In most vector instruction formats [1] V1, V2, V3, and V4 directly
212  * correspond to @v1, @v2, @v3, and @v4. But there are exceptions, such as but
219 .macro	RXB	rxb v1 v2=0 v3=0 v4=0
221 	.if \v1 & 0x10
238  * @v1:		First vector register designated operand (for RXB)
243  * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
246 .macro	MRXB	m v1 v2=0 v3=0 v4=0
248 	RXB	rxb, \v1, \v2, \v3, \v4
256  * @v1:		First vector register designated operand (for RXB)
261  * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
264 .macro	MRXBOPC	m opc v1 v2=0 v3=0 v4=0
265 	MRXB	\m, \v1, \v2, \v3, \v4
273 	VX_NUM	v1, \vr
274 	.word	(0xE700 | ((v1&15) << 4))
276 	MRXBOPC	0, 0x44, v1
287 	VX_NUM	v1, \v
290 	.word	0xE700 | ((v1&15) << 4) | r3
292 	MRXBOPC	\m, 0x22, v1
308 .macro	VLR	v1, v2
309 	VX_NUM	v1, \v1
311 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
313 	MRXBOPC	0, 0x56, v1, v2
318 	VX_NUM	v1, \v
321 	.word	0xE700 | ((v1&15) << 4) | x2
323 	MRXBOPC 0, 0x06, v1
328 	VX_NUM	v1, \vr1
331 	.word	0xE700 | ((v1&15) << 4) | x2
333 	MRXBOPC	\m3, \opc, v1
350 	VX_NUM	v1, \vr1
351 	.word	0xE700 | ((v1&15) << 4)
353 	MRXBOPC	\m3, \opc, v1
392 	VX_NUM	v1, \vfrom
395 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
397 	MRXBOPC	\hint, 0x36, v1, v3
402 	VX_NUM	v1, \vr1
405 	.word	0xE700 | ((v1&15) << 4) | (x2&15)
407 	MRXBOPC	0, 0x0E, v1
412 	VX_NUM	v1, \vr1
415 	.word	0xE600 | ((v1&15) << 4) | (x2&15)
417 	MRXBOPC	\m, 0x0E, v1
434 	VX_NUM	v1, \vfrom
437 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
439 	MRXBOPC	\hint, 0x3E, v1, v3
444 	VX_NUM	v1, \vr1
448 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
450 	MRXBOPC	(v4&15), 0x8C, v1, v2, v3, v4
455 	VX_NUM	v1, \vr1
457 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
459 	MRXBOPC	\m3, 0xD4, v1, v2
473 	VX_NUM	v1, \vr1
476 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
478 	MRXBOPC	\m4, 0x84, v1, v2, v3
483 	VX_NUM	v1, \vr1
485 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
487 	MRXBOPC	\m4, 0x4D, v1, v3
504 	VX_NUM	v1, \vr1
507 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
509 	MRXBOPC	\m4, 0x61, v1, v2, v3
526 	VX_NUM	v1, \vr1
529 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
531 	MRXBOPC	\m4, 0x60, v1, v2, v3
548 	VX_NUM	v1, \v
551 	.word	0xE700 | ((v1&15) << 4) | r3
553 	MRXBOPC 0, 0x37, v1
558 	VX_NUM	v1, \v
561 	.word	0xE700 | ((v1&15) << 4) | r3
563 	MRXBOPC 0, 0x3f, v1
570 	VX_NUM	v1, \vr1
573 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
575 	MRXBOPC	0, 0x68, v1, v2, v3
580 	VX_NUM	v1, \vr1
583 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
585 	MRXBOPC 0, 0x66, v1, v2, v3
590 	VX_NUM	v1, \vr1
593 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
595 	MRXBOPC	0, 0x6D, v1, v2, v3
600 	VX_NUM	v1, \vr1
603 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
605 	MRXBOPC	\m4, 0xB4, v1, v2, v3
622 	VX_NUM	v1, \vr1
626 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
628 	MRXBOPC	(v4&15), 0xBC, v1, v2, v3, v4
645 	VX_NUM	v1, \vr1
648 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
650 	MRXBOPC	0, 0x7D, v1, v2, v3
655 	VX_NUM	v1, \vr1
656 	.word	0xE700 | ((v1&15) << 4)
658 	MRXBOPC	\m3, 0x45, v1
675 	VX_NUM	v1, \vr1
678 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
680 	MRXBOPC	\m4, 0xF3, v1, v2, v3
700 	VX_NUM	v1, \vr1
703 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
705 	MRXBOPC \m4, 0x7A, v1, v2, v3
723 	VX_NUM	v1, \vr1
726 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
728 	MRXBOPC	\m4, 0x33, v1, v3
745 	VX_NUM	v1, \vr1
748 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
750 	MRXBOPC	0, 0x77, v1, v2, v3