Lines Matching +full:- +full:12 +full:v
1 /* SPDX-License-Identifier: GPL-2.0 */
16 #error only <asm/fpu-insn.h> can be included directly
23 /* GR_NUM - Retrieve general-purpose register number
67 \opd = 12
83 /* VX_NUM - Retrieve vector register number
131 \opd = 12
195 /* RXB - Compute most significant bit used vector registers
200 * are stored in instruction bits 8-11.
203 * are stored in instruction bits 12-15.
206 * are stored in instruction bits 16-19.
209 * are stored in instruction bits 32-35.
213 * not limited to the vector instruction formats VRR-g, VRR-h, VRS-a, VRS-d,
235 /* MRXB - Generate Element Size Control and RXB value
252 /* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields
286 .macro VLVG v, gr, disp, m
287 VX_NUM v1, \v
291 .word (b2 << 12) | (\disp)
294 .macro VLVGB v, gr, index, base
295 VLVG \v, \gr, \index, \base, 0
297 .macro VLVGH v, gr, index
298 VLVG \v, \gr, \index, 1
300 .macro VLVGF v, gr, index
301 VLVG \v, \gr, \index, 2
303 .macro VLVGG v, gr, index
304 VLVG \v, \gr, \index, 3
317 .macro VL v, disp, index="%r0", base
318 VX_NUM v1, \v
322 .word (b2 << 12) | (\disp)
332 .word (b2 << 12) | (\disp)
374 .word (b2 << 12) | (\disp)
396 .word (b2 << 12) | (\disp)
406 .word (b2 << 12) | (\disp)
416 .word (b2 << 12) | (\disp)
438 .word (b2 << 12) | (\disp)
449 .word ((v3&15) << 12)
477 .word ((v3&15) << 12)
508 .word ((v3&15) << 12)
530 .word ((v3&15) << 12)
547 .macro VLL v, gr, disp, base
548 VX_NUM v1, \v
552 .word (b2 << 12) | (\disp)
557 .macro VSTL v, gr, disp, base
558 VX_NUM v1, \v
562 .word (b2 << 12) | (\disp)
574 .word ((v3&15) << 12)
584 .word ((v3&15) << 12)
594 .word ((v3&15) << 12)
604 .word ((v3&15) << 12)
627 .word ((v3&15) << 12) | (\m5 << 8)
649 .word ((v3&15) << 12)
679 .word ((v3&15) << 12)
704 .word ((v3&15) << 12)
727 .word (b2 << 12) | (\disp)
749 .word ((v3&15) << 12) | (\imm4)