Lines Matching +full:riscv +full:- +full:j +full:- +full:extension

1 // SPDX-License-Identifier: GPL-2.0-only
35  * Performs an icache flush for the given MM context.  RISC-V has no direct
39  * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
52 	mask = &mm->context.icache_stale_mask;  in flush_icache_mm()
65 	if (mm == current->active_mm && local) {  in flush_icache_mm()
91 	if (!test_bit(PG_dcache_clean, &folio->flags)) {  in flush_icache_pte()
93 		set_bit(PG_dcache_clean, &folio->flags);  in flush_icache_pte()
136 			/* set block-size for cbom and/or cboz extension if available */  in riscv_init_cbo_blocksizes()
137 			cbo_get_block_size(node, "riscv,cbom-block-size",  in riscv_init_cbo_blocksizes()
139 			cbo_get_block_size(node, "riscv,cboz-block-size",  in riscv_init_cbo_blocksizes()
171 	mask = &current->mm->context.icache_stale_mask;  in set_icache_stale_mask()
181  * riscv_set_icache_flush_ctx() - Enable/disable icache flushing instructions in
215  * instruction. This must be performed by the user-space program.
217  * In per-thread context (eg. ``scope == PR_RISCV_SCOPE_PER_THREAD``) only the
232 			current->mm->context.force_icache_flush = true;  in riscv_set_icache_flush_ctx()
235 			current->thread.force_icache_flush = true;  in riscv_set_icache_flush_ctx()
238 			return -EINVAL;  in riscv_set_icache_flush_ctx()
245 			current->mm->context.force_icache_flush = false;  in riscv_set_icache_flush_ctx()
249 			current->thread.force_icache_flush = false;  in riscv_set_icache_flush_ctx()
252 			return -EINVAL;  in riscv_set_icache_flush_ctx()
256 		return -EINVAL;  in riscv_set_icache_flush_ctx()
265 		return -EINVAL;  in riscv_set_icache_flush_ctx()