1 // SPDX-License-Identifier: GPL-2.0-only
30 	 * the IPI. The RISC-V spec states that a hart must execute a data fence  in flush_icache_all()
34 	 * IPIs on RISC-V are triggered by MMIO writes to either CLINT or  in flush_icache_all()
35 	 * S-IMSIC, so the fence ensures previous data writes "happen before"  in flush_icache_all()
48  * Performs an icache flush for the given MM context.  RISC-V has no direct
52  * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
65 	mask = &mm->context.icache_stale_mask;  in flush_icache_mm()
78 	if (mm == current->active_mm && local) {  in flush_icache_mm()
104 	if (!test_bit(PG_dcache_clean, &folio->flags.f)) {  in flush_icache_pte()
106 		set_bit(PG_dcache_clean, &folio->flags.f);  in flush_icache_pte()
152 			/* set block-size for cbom and/or cboz extension if available */  in riscv_init_cbo_blocksizes()
153 			cbo_get_block_size(node, "riscv,cbom-block-size",  in riscv_init_cbo_blocksizes()
155 			cbo_get_block_size(node, "riscv,cboz-block-size",  in riscv_init_cbo_blocksizes()
157 			cbo_get_block_size(node, "riscv,cbop-block-size",  in riscv_init_cbo_blocksizes()
192 	mask = &current->mm->context.icache_stale_mask;  in set_icache_stale_mask()
202  * riscv_set_icache_flush_ctx() - Enable/disable icache flushing instructions in
236  * instruction. This must be performed by the user-space program.
238  * In per-thread context (eg. ``scope == PR_RISCV_SCOPE_PER_THREAD``) only the
253 			current->mm->context.force_icache_flush = true;  in riscv_set_icache_flush_ctx()
256 			current->thread.force_icache_flush = true;  in riscv_set_icache_flush_ctx()
259 			return -EINVAL;  in riscv_set_icache_flush_ctx()
266 			current->mm->context.force_icache_flush = false;  in riscv_set_icache_flush_ctx()
270 			current->thread.force_icache_flush = false;  in riscv_set_icache_flush_ctx()
273 			return -EINVAL;  in riscv_set_icache_flush_ctx()
277 		return -EINVAL;  in riscv_set_icache_flush_ctx()
286 		return -EINVAL;  in riscv_set_icache_flush_ctx()