Lines Matching +full:isa +full:- +full:extensions
1 // SPDX-License-Identifier: GPL-2.0
25 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */
27 /* Single letter extensions (alphabetically sorted) */
36 /* Multi letter extensions (alphabetically sorted) */
125 /* Extensions which don't have any mechanism to disable */ in kvm_riscv_vcpu_isa_disable_allowed()
181 /* Extensions which can be disabled using Smstateen */ in kvm_riscv_vcpu_isa_disable_allowed()
199 set_bit(host_isa, vcpu->arch.isa); in kvm_riscv_vcpu_setup_isa()
207 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_config()
208 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_config()
213 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_config()
214 return -EINVAL; in kvm_riscv_vcpu_get_reg_config()
217 case KVM_REG_RISCV_CONFIG_REG(isa): in kvm_riscv_vcpu_get_reg_config()
218 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config()
221 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in kvm_riscv_vcpu_get_reg_config()
222 return -ENOENT; in kvm_riscv_vcpu_get_reg_config()
226 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in kvm_riscv_vcpu_get_reg_config()
227 return -ENOENT; in kvm_riscv_vcpu_get_reg_config()
231 reg_val = vcpu->arch.mvendorid; in kvm_riscv_vcpu_get_reg_config()
234 reg_val = vcpu->arch.marchid; in kvm_riscv_vcpu_get_reg_config()
237 reg_val = vcpu->arch.mimpid; in kvm_riscv_vcpu_get_reg_config()
243 return -ENOENT; in kvm_riscv_vcpu_get_reg_config()
246 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_config()
247 return -EFAULT; in kvm_riscv_vcpu_get_reg_config()
256 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_config()
257 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_config()
262 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_config()
263 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
265 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_config()
266 return -EFAULT; in kvm_riscv_vcpu_set_reg_config()
269 case KVM_REG_RISCV_CONFIG_REG(isa): in kvm_riscv_vcpu_set_reg_config()
272 * single letter extensions. in kvm_riscv_vcpu_set_reg_config()
275 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
281 if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK)) in kvm_riscv_vcpu_set_reg_config()
284 if (!vcpu->arch.ran_atleast_once) { in kvm_riscv_vcpu_set_reg_config()
285 /* Ignore the enable/disable request for certain extensions */ in kvm_riscv_vcpu_set_reg_config()
300 /* Do not modify anything beyond single letter extensions */ in kvm_riscv_vcpu_set_reg_config()
301 reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) | in kvm_riscv_vcpu_set_reg_config()
303 vcpu->arch.isa[0] = reg_val; in kvm_riscv_vcpu_set_reg_config()
306 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
310 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in kvm_riscv_vcpu_set_reg_config()
311 return -ENOENT; in kvm_riscv_vcpu_set_reg_config()
313 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
316 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in kvm_riscv_vcpu_set_reg_config()
317 return -ENOENT; in kvm_riscv_vcpu_set_reg_config()
319 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
322 if (reg_val == vcpu->arch.mvendorid) in kvm_riscv_vcpu_set_reg_config()
324 if (!vcpu->arch.ran_atleast_once) in kvm_riscv_vcpu_set_reg_config()
325 vcpu->arch.mvendorid = reg_val; in kvm_riscv_vcpu_set_reg_config()
327 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
330 if (reg_val == vcpu->arch.marchid) in kvm_riscv_vcpu_set_reg_config()
332 if (!vcpu->arch.ran_atleast_once) in kvm_riscv_vcpu_set_reg_config()
333 vcpu->arch.marchid = reg_val; in kvm_riscv_vcpu_set_reg_config()
335 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
338 if (reg_val == vcpu->arch.mimpid) in kvm_riscv_vcpu_set_reg_config()
340 if (!vcpu->arch.ran_atleast_once) in kvm_riscv_vcpu_set_reg_config()
341 vcpu->arch.mimpid = reg_val; in kvm_riscv_vcpu_set_reg_config()
343 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
347 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
350 return -ENOENT; in kvm_riscv_vcpu_set_reg_config()
359 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_vcpu_get_reg_core()
361 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_core()
362 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_core()
367 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_core()
368 return -EINVAL; in kvm_riscv_vcpu_get_reg_core()
370 return -ENOENT; in kvm_riscv_vcpu_get_reg_core()
373 reg_val = cntx->sepc; in kvm_riscv_vcpu_get_reg_core()
378 reg_val = (cntx->sstatus & SR_SPP) ? in kvm_riscv_vcpu_get_reg_core()
381 return -ENOENT; in kvm_riscv_vcpu_get_reg_core()
383 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_core()
384 return -EFAULT; in kvm_riscv_vcpu_get_reg_core()
392 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_vcpu_set_reg_core()
394 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_core()
395 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_core()
400 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_core()
401 return -EINVAL; in kvm_riscv_vcpu_set_reg_core()
403 return -ENOENT; in kvm_riscv_vcpu_set_reg_core()
405 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_core()
406 return -EFAULT; in kvm_riscv_vcpu_set_reg_core()
409 cntx->sepc = reg_val; in kvm_riscv_vcpu_set_reg_core()
415 cntx->sstatus |= SR_SPP; in kvm_riscv_vcpu_set_reg_core()
417 cntx->sstatus &= ~SR_SPP; in kvm_riscv_vcpu_set_reg_core()
419 return -ENOENT; in kvm_riscv_vcpu_set_reg_core()
428 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_general_get_csr()
431 return -ENOENT; in kvm_riscv_vcpu_general_get_csr()
435 *out_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK; in kvm_riscv_vcpu_general_get_csr()
436 *out_val |= csr->hvip & ~IRQ_LOCAL_MASK; in kvm_riscv_vcpu_general_get_csr()
447 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_general_set_csr()
450 return -ENOENT; in kvm_riscv_vcpu_general_set_csr()
460 WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0); in kvm_riscv_vcpu_general_set_csr()
469 struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; in kvm_riscv_vcpu_smstateen_set_csr()
473 return -EINVAL; in kvm_riscv_vcpu_smstateen_set_csr()
483 struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; in kvm_riscv_vcpu_smstateen_get_csr()
487 return -EINVAL; in kvm_riscv_vcpu_smstateen_get_csr()
498 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_csr()
499 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_csr()
504 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_csr()
505 return -EINVAL; in kvm_riscv_vcpu_get_reg_csr()
517 rc = -EINVAL; in kvm_riscv_vcpu_get_reg_csr()
523 rc = -ENOENT; in kvm_riscv_vcpu_get_reg_csr()
529 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_csr()
530 return -EFAULT; in kvm_riscv_vcpu_get_reg_csr()
540 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_csr()
541 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_csr()
546 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_csr()
547 return -EINVAL; in kvm_riscv_vcpu_set_reg_csr()
549 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_csr()
550 return -EFAULT; in kvm_riscv_vcpu_set_reg_csr()
562 rc = -EINVAL; in kvm_riscv_vcpu_set_reg_csr()
568 rc = -ENOENT; in kvm_riscv_vcpu_set_reg_csr()
585 return -ENOENT; in riscv_vcpu_get_isa_ext_single()
589 return -ENOENT; in riscv_vcpu_get_isa_ext_single()
592 if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext)) in riscv_vcpu_get_isa_ext_single()
606 return -ENOENT; in riscv_vcpu_set_isa_ext_single()
610 return -ENOENT; in riscv_vcpu_set_isa_ext_single()
612 if (reg_val == test_bit(host_isa_ext, vcpu->arch.isa)) in riscv_vcpu_set_isa_ext_single()
615 if (!vcpu->arch.ran_atleast_once) { in riscv_vcpu_set_isa_ext_single()
617 * All multi-letter extension and a few single letter in riscv_vcpu_set_isa_ext_single()
622 set_bit(host_isa_ext, vcpu->arch.isa); in riscv_vcpu_set_isa_ext_single()
625 clear_bit(host_isa_ext, vcpu->arch.isa); in riscv_vcpu_set_isa_ext_single()
627 return -EINVAL; in riscv_vcpu_set_isa_ext_single()
630 return -EBUSY; in riscv_vcpu_set_isa_ext_single()
643 return -ENOENT; in riscv_vcpu_get_isa_ext_multi()
666 return -ENOENT; in riscv_vcpu_set_isa_ext_multi()
684 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_isa_ext()
685 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_isa_ext()
690 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_isa_ext()
691 return -EINVAL; in kvm_riscv_vcpu_get_reg_isa_ext()
708 rc = -ENOENT; in kvm_riscv_vcpu_get_reg_isa_ext()
713 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_isa_ext()
714 return -EFAULT; in kvm_riscv_vcpu_get_reg_isa_ext()
723 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_isa_ext()
724 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_isa_ext()
729 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_isa_ext()
730 return -EINVAL; in kvm_riscv_vcpu_set_reg_isa_ext()
735 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_isa_ext()
736 return -EFAULT; in kvm_riscv_vcpu_set_reg_isa_ext()
746 return -ENOENT; in kvm_riscv_vcpu_set_reg_isa_ext()
767 !riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in copy_config_reg_indices()
770 !riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in copy_config_reg_indices()
778 return -EFAULT; in copy_config_reg_indices()
809 return -EFAULT; in copy_core_reg_indices()
821 if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA)) in num_csr_regs()
823 if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN)) in num_csr_regs()
844 return -EFAULT; in copy_csr_reg_indices()
850 if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA)) { in copy_csr_reg_indices()
861 return -EFAULT; in copy_csr_reg_indices()
868 if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN)) { in copy_csr_reg_indices()
879 return -EFAULT; in copy_csr_reg_indices()
903 return -EFAULT; in copy_timer_reg_indices()
913 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in num_fp_f_regs()
915 if (riscv_isa_extension_available(vcpu->arch.isa, f)) in num_fp_f_regs()
916 return sizeof(cntx->fp.f) / sizeof(u32); in num_fp_f_regs()
932 return -EFAULT; in copy_fp_f_reg_indices()
942 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in num_fp_d_regs()
944 if (riscv_isa_extension_available(vcpu->arch.isa, d)) in num_fp_d_regs()
945 return sizeof(cntx->fp.d.f) / sizeof(u64) + 1; in num_fp_d_regs()
958 for (i = 0; i < n-1; i++) { in copy_fp_d_reg_indices()
964 return -EFAULT; in copy_fp_d_reg_indices()
973 return -EFAULT; in copy_fp_d_reg_indices()
997 return -EFAULT; in copy_isa_ext_reg_indices()
1027 return -EFAULT; in copy_sbi_ext_reg_indices()
1044 struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; in copy_sbi_reg_indices()
1047 if (scontext->ext_status[KVM_RISCV_SBI_EXT_STA] == KVM_RISCV_SBI_EXT_STATUS_ENABLED) { in copy_sbi_reg_indices()
1058 return -EFAULT; in copy_sbi_reg_indices()
1076 if (!riscv_isa_extension_available(vcpu->arch.isa, v)) in num_vector_regs()
1086 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in copy_vector_reg_indices()
1101 return -EFAULT; in copy_vector_reg_indices()
1107 size = __builtin_ctzl(cntx->vector.vlenb); in copy_vector_reg_indices()
1115 return -EFAULT; in copy_vector_reg_indices()
1124 * kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG
1147 * kvm_riscv_vcpu_copy_reg_indices - get indices of all registers.
1210 switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { in kvm_riscv_vcpu_set_reg()
1237 return -ENOENT; in kvm_riscv_vcpu_set_reg()
1243 switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { in kvm_riscv_vcpu_get_reg()
1270 return -ENOENT; in kvm_riscv_vcpu_get_reg()