1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/entry-common.h>
95 #define XLEN				64  macro
98 #define XLEN				32  macro
100 #define REGBYTES			(1 << LOG_REGBYTES)
101 #define XLEN_MINUS_16			((XLEN) - 16)
108 #define RV_X(x, s, n)			(((x) >> (s)) & ((1 << (n)) - 1))
109 #define RVC_LW_IMM(x)			((RV_X(x, 6, 1) << 2) | \
111 					 (RV_X(x, 5, 1) << 6))
115 					 (RV_X(x, 12, 1) << 5) | \
118 					 (RV_X(x, 12, 1) << 5) | \
129 	((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
132 	((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
135 	(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
155 #define PRECISION_D 1
169 	regs->status |= SR_FS_DIRTY;  in set_f32_rd()
187 	regs->status |= SR_FS_DIRTY;  in set_f64_rd()
202 	regs->status |= SR_FS_DIRTY;  in get_f64_rs()
217 	regs->status |= SR_FS_DIRTY;  in get_f64_rs()
233 	regs->status |= SR_FS_DIRTY;  in get_f32_rs()
288 			return -EFAULT;  in get_insn()
300 			return -EFAULT;  in get_insn()
306 			return -EFAULT;  in get_insn()
325 int unaligned_enabled __read_mostly = 1;	/* Enabled by default */
330 	unsigned long epc = regs->epc;  in handle_vector_misaligned_load()
334 		return -1;  in handle_vector_misaligned_load()
339 		regs->epc = epc + INSN_LEN(insn);  in handle_vector_misaligned_load()
344 	regs->epc = epc;  in handle_vector_misaligned_load()
345 	return -1;  in handle_vector_misaligned_load()
350 	return -1;  in handle_vector_misaligned_load()
357 	unsigned long epc = regs->epc;  in handle_scalar_misaligned_load()
359 	unsigned long addr = regs->badaddr;  in handle_scalar_misaligned_load()
362 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);  in handle_scalar_misaligned_load()
369 		return -1;  in handle_scalar_misaligned_load()
371 	if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS))  in handle_scalar_misaligned_load()
372 		return -1;  in handle_scalar_misaligned_load()
375 		return -1;  in handle_scalar_misaligned_load()
377 	regs->epc = 0;  in handle_scalar_misaligned_load()
381 		shift = 8 * (sizeof(unsigned long) - len);  in handle_scalar_misaligned_load()
385 		shift = 8 * (sizeof(unsigned long) - len);  in handle_scalar_misaligned_load()
390 		fp = 1;  in handle_scalar_misaligned_load()
393 		fp = 1;  in handle_scalar_misaligned_load()
397 		shift = 8 * (sizeof(unsigned long) - len);  in handle_scalar_misaligned_load()
403 		shift = 8 * (sizeof(unsigned long) - len);  in handle_scalar_misaligned_load()
408 		shift = 8 * (sizeof(unsigned long) - len);  in handle_scalar_misaligned_load()
412 		shift = 8 * (sizeof(unsigned long) - len);  in handle_scalar_misaligned_load()
417 		shift = 8 * (sizeof(unsigned long) - len);  in handle_scalar_misaligned_load()
419 		fp = 1;  in handle_scalar_misaligned_load()
423 		fp = 1;  in handle_scalar_misaligned_load()
427 		fp = 1;  in handle_scalar_misaligned_load()
431 		fp = 1;  in handle_scalar_misaligned_load()
435 		regs->epc = epc;  in handle_scalar_misaligned_load()
436 		return -1;  in handle_scalar_misaligned_load()
440 		return -EOPNOTSUPP;  in handle_scalar_misaligned_load()
445 			return -1;  in handle_scalar_misaligned_load()
457 	regs->epc = epc + INSN_LEN(insn);  in handle_scalar_misaligned_load()
465 	unsigned long epc = regs->epc;  in handle_scalar_misaligned_store()
467 	unsigned long addr = regs->badaddr;  in handle_scalar_misaligned_store()
470 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);  in handle_scalar_misaligned_store()
473 		return -1;  in handle_scalar_misaligned_store()
475 	if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS))  in handle_scalar_misaligned_store()
476 		return -1;  in handle_scalar_misaligned_store()
479 		return -1;  in handle_scalar_misaligned_store()
481 	regs->epc = 0;  in handle_scalar_misaligned_store()
492 		fp = 1;  in handle_scalar_misaligned_store()
496 		fp = 1;  in handle_scalar_misaligned_store()
516 		fp = 1;  in handle_scalar_misaligned_store()
520 		fp = 1;  in handle_scalar_misaligned_store()
525 		fp = 1;  in handle_scalar_misaligned_store()
529 		fp = 1;  in handle_scalar_misaligned_store()
534 		regs->epc = epc;  in handle_scalar_misaligned_store()
535 		return -1;  in handle_scalar_misaligned_store()
539 		return -EOPNOTSUPP;  in handle_scalar_misaligned_store()
543 			return -1;  in handle_scalar_misaligned_store()
548 	regs->epc = epc + INSN_LEN(insn);  in handle_scalar_misaligned_store()
555 	unsigned long epc = regs->epc;  in handle_misaligned_load()
560 			return -1;  in handle_misaligned_load()
569 	return -1;  in handle_misaligned_load()
577 	return -1;  in handle_misaligned_store()
590 	 * In pre-13.0.0 versions of GCC, vector registers cannot appear in  in check_vector_unaligned_access_emulated()
601 		"       vsetivli zero, 1, e16, m1, ta, ma\n\t"	// Vectors of 16b  in check_vector_unaligned_access_emulated()
604 		: : [ptr] "r" ((u8 *)&tmp_var + 1));  in check_vector_unaligned_access_emulated()
647 		"       "REG_L" %[tmp], 1(%[ptr])\n"  in check_unaligned_access_emulated()