Lines Matching +full:riscv +full:- +full:svvptc
1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
43 /* Per-cpu ISA extensions. */
49 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
89 return -EPROBE_DEFER; in riscv_ext_f_depends()
96 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
97 return -EINVAL; in riscv_ext_zicbom_validate()
100 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate()
101 return -EINVAL; in riscv_ext_zicbom_validate()
112 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); in riscv_ext_zicboz_validate()
113 return -EINVAL; in riscv_ext_zicboz_validate()
116 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n"); in riscv_ext_zicboz_validate()
117 return -EINVAL; in riscv_ext_zicboz_validate()
127 pr_err("Zicbop detected in ISA string, disabling as no cbop-block-size found\n"); in riscv_ext_zicbop_validate()
128 return -EINVAL; in riscv_ext_zicbop_validate()
131 pr_err("Zicbop disabled as cbop-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbop_validate()
132 return -EINVAL; in riscv_ext_zicbop_validate()
142 return -EINVAL; in riscv_ext_f_validate()
150 return -EINVAL; in riscv_ext_f_validate()
160 return -EINVAL; in riscv_ext_d_validate()
169 return -EINVAL; in riscv_ext_vector_x_validate()
178 return -EINVAL; in riscv_ext_vector_float_validate()
181 return -EINVAL; in riscv_ext_vector_float_validate()
192 return -EINVAL; in riscv_ext_vector_float_validate()
201 return -EINVAL; in riscv_ext_vector_crypto_validate()
206 * enabled, which in-turn means that vector is usable in this kernel in riscv_ext_vector_crypto_validate()
209 return -EPROBE_DEFER; in riscv_ext_vector_crypto_validate()
220 return -EPROBE_DEFER; in riscv_ext_zca_depends()
229 return -EPROBE_DEFER; in riscv_ext_zcd_validate()
236 return -EINVAL; in riscv_ext_zcf_validate()
242 return -EPROBE_DEFER; in riscv_ext_zcf_validate()
249 return -EINVAL; in riscv_vector_f_validate()
254 return -EPROBE_DEFER; in riscv_vector_f_validate()
264 return -EPROBE_DEFER; in riscv_ext_zvfbfwma_validate()
272 return -EOPNOTSUPP; in riscv_ext_svadu_validate()
387 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
398 * - C always implies Zca
399 * - C+F implies Zcf (RV32 only)
400 * - C+D implies Zcd
415 * Ordinarily, for in-kernel data structures, this order is unimportant but
421 * 1. All multi-letter extensions must be separated from other extensions by an
425 * single-letter extensions and before any higher-privileged extensions.
432 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
433 * after standard unprivileged extensions. If multiple supervisor-level
436 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
437 * after any lower-privileged, standard extensions. If multiple
438 * machine-level extensions are listed, they must be ordered
441 * 5. Non-standard extensions (starting with 'X') must be listed after all
442 * standard extensions. If multiple non-standard extensions are listed, they
542 __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
549 if (ext->id != RISCV_ISA_EXT_INVALID) in riscv_isa_set_ext()
550 set_bit(ext->id, bitmap); in riscv_isa_set_ext()
552 for (int i = 0; i < ext->subset_ext_size; i++) { in riscv_isa_set_ext()
553 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID) in riscv_isa_set_ext()
554 set_bit(ext->subset_ext_ids[i], bitmap); in riscv_isa_set_ext()
587 if (max_loop_count-- < 0) { in riscv_resolve_isa()
595 if (ext && ext->validate) { in riscv_resolve_isa()
596 ret = ext->validate(ext, resolved_isa); in riscv_resolve_isa()
597 if (ret == -EPROBE_DEFER) { in riscv_resolve_isa()
623 if ((name_end - name == strlen(ext->name)) && in match_isa_ext()
624 !strncasecmp(name, ext->name, name_end - name)) { in match_isa_ext()
650 pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead."); in riscv_parse_isa_string()
653 * As multi-letter extensions must be split from other multi-letter in riscv_parse_isa_string()
654 * extensions with an "_", the end of a multi-letter extension will in riscv_parse_isa_string()
656 * multi-letter extension. in riscv_parse_isa_string()
664 * Workaround for invalid single-letter 's' & 'u' (QEMU). in riscv_parse_isa_string()
667 * multi-letter extension in the ISA string begins with in riscv_parse_isa_string()
670 if (ext[-1] != '_' && ext[1] == 'u') { in riscv_parse_isa_string()
681 * As multi-letter extensions must be split from other multi-letter in riscv_parse_isa_string()
682 * extensions with an "_", the end of a multi-letter extension will in riscv_parse_isa_string()
684 * multi-letter extension. in riscv_parse_isa_string()
695 * A simple re-increment solves this problem. in riscv_parse_isa_string()
705 if (!isdigit(ext_end[-1])) in riscv_parse_isa_string()
708 while (isdigit(*--ext_end)) in riscv_parse_isa_string()
711 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { in riscv_parse_isa_string()
716 while (isdigit(*--ext_end)) in riscv_parse_isa_string()
723 * Things are a little easier for single-letter extensions, as they in riscv_parse_isa_string()
730 * If we are already on a non-digit, there is nothing to do. Either in riscv_parse_isa_string()
731 * we have a multi-letter extension's _, or the start of an in riscv_parse_isa_string()
755 --isa; in riscv_parse_isa_string()
768 * on meeting a non-alphanumeric character, an extra increment is needed in riscv_parse_isa_string()
769 * where the succeeding extension is a multi-letter prefixed with an "_". in riscv_parse_isa_string()
813 rc = of_property_read_string(node, "riscv,isa", &isa); in riscv_fill_hwcap_from_isa_string()
816 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); in riscv_fill_hwcap_from_isa_string()
822 pr_warn("Unable to get ISA for the hart - %d\n", cpu); in riscv_fill_hwcap_from_isa_string()
831 * port & dt-bindings were upstreamed, and so can be set in riscv_fill_hwcap_from_isa_string()
832 * unconditionally where `i` is in riscv,isa on DT systems. in riscv_fill_hwcap_from_isa_string()
843 * just the standard V-1.0 but vendors aren't well behaved. in riscv_fill_hwcap_from_isa_string()
844 * Many vendors with T-Head CPU cores which implement the 0.7.1 in riscv_fill_hwcap_from_isa_string()
846 * CPU cores with the ratified spec will contain non-zero in riscv_fill_hwcap_from_isa_string()
854 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); in riscv_fill_hwcap_from_isa_string()
867 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_isa_string()
869 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_isa_string()
884 for (int j = 0; j < ext_list->ext_data_count; j++) { in riscv_fill_cpu_vendor_ext()
885 const struct riscv_isa_ext_data ext = ext_list->ext_data[j]; in riscv_fill_cpu_vendor_ext()
886 struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu]; in riscv_fill_cpu_vendor_ext()
888 if (of_property_match_string(cpu_node, "riscv,isa-extensions", in riscv_fill_cpu_vendor_ext()
898 set_bit(ext.subset_ext_ids[k], isavendorinfo->isa); in riscv_fill_cpu_vendor_ext()
900 set_bit(ext.id, isavendorinfo->isa); in riscv_fill_cpu_vendor_ext()
917 if (!ext_list->is_initialized) { in riscv_fill_vendor_ext_list()
918 bitmap_copy(ext_list->all_harts_isa_bitmap.isa, in riscv_fill_vendor_ext_list()
919 ext_list->per_hart_isa_bitmap[cpu].isa, in riscv_fill_vendor_ext_list()
921 ext_list->is_initialized = true; in riscv_fill_vendor_ext_list()
923 bitmap_and(ext_list->all_harts_isa_bitmap.isa, in riscv_fill_vendor_ext_list()
924 ext_list->all_harts_isa_bitmap.isa, in riscv_fill_vendor_ext_list()
925 ext_list->per_hart_isa_bitmap[cpu].isa, in riscv_fill_vendor_ext_list()
947 return -ENOENT; in has_thead_homogeneous_vlenb()
954 return -ENOENT; in has_thead_homogeneous_vlenb()
960 return -ENOENT; in has_thead_homogeneous_vlenb()
988 if (!of_property_present(cpu_node, "riscv,isa-extensions")) { in riscv_fill_hwcap_from_ext_list()
996 if (of_property_match_string(cpu_node, "riscv,isa-extensions", in riscv_fill_hwcap_from_ext_list()
997 ext->property) < 0) in riscv_fill_hwcap_from_ext_list()
1003 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); in riscv_fill_hwcap_from_ext_list()
1018 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_ext_list()
1020 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_ext_list()
1037 return -ENOENT; in riscv_fill_hwcap_from_ext_list()
1060 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; in riscv_fill_hwcap()
1061 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; in riscv_fill_hwcap()
1062 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; in riscv_fill_hwcap()
1063 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; in riscv_fill_hwcap()
1064 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; in riscv_fill_hwcap()
1065 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; in riscv_fill_hwcap()
1066 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; in riscv_fill_hwcap()
1074 pr_info("Falling back to deprecated \"riscv,isa\"\n"); in riscv_fill_hwcap()
1100 pr_info("riscv: base ISA extensions %s\n", print_str); in riscv_fill_hwcap()
1106 pr_info("riscv: ELF capabilities %s\n", print_str); in riscv_fill_hwcap()
1113 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); in riscv_get_elf_hwcap()
1124 current->thread.envcfg |= ENVCFG_CBZE; in riscv_user_isa_enable()
1129 current->thread.envcfg |= ENVCFG_CBCFE; in riscv_user_isa_enable()
1142 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
1143 * patch site is for an erratum, identified by the 32-bit patch ID. When
1145 * further break down patch ID into two 16-bit numbers. The lower 16 bits
1149 * patching on a per-site basis will provide non-zero values and implement
1184 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); in riscv_cpufeature_patch_func()
1185 vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id); in riscv_cpufeature_patch_func()
1200 if (alt->vendor_id != 0) in riscv_cpufeature_patch_func()
1206 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); in riscv_cpufeature_patch_func()
1211 id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) in riscv_cpufeature_patch_func()
1222 patch_text_nosync(oldptr, altptr, alt->alt_len); in riscv_cpufeature_patch_func()
1223 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); in riscv_cpufeature_patch_func()