Lines Matching +full:riscv +full:- +full:j +full:- +full:extension
1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <asm/text-patching.h>
30 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
39 /* Per-cpu ISA extensions. */
43 * riscv_isa_extension_base() - Get base extension word
46 * Return: base extension word as unsigned long value
59 * __riscv_isa_extension_available() - Check whether given extension
63 * @bit: bit position of the desired extension
83 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
84 return -EINVAL; in riscv_ext_zicbom_validate()
87 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate()
88 return -EINVAL; in riscv_ext_zicbom_validate()
97 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); in riscv_ext_zicboz_validate()
98 return -EINVAL; in riscv_ext_zicboz_validate()
101 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n"); in riscv_ext_zicboz_validate()
102 return -EINVAL; in riscv_ext_zicboz_validate()
114 return -EPROBE_DEFER; in riscv_ext_zca_depends()
123 return -EPROBE_DEFER; in riscv_ext_zcd_validate()
130 return -EINVAL; in riscv_ext_zcf_validate()
136 return -EPROBE_DEFER; in riscv_ext_zcf_validate()
144 return -EOPNOTSUPP; in riscv_ext_svadu_validate()
254 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
255 * privileged ISA, the existence of the CSRs is implied by any extension which
256 * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the
265 * - C always implies Zca
266 * - C+F implies Zcf (RV32 only)
267 * - C+D implies Zcd
279 * The canonical order of ISA extension names in the ISA string is defined in
282 * Ordinarily, for in-kernel data structures, this order is unimportant but
288 * 1. All multi-letter extensions must be separated from other extensions by an
292 * single-letter extensions and before any higher-privileged extensions.
295 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
299 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
300 * after standard unprivileged extensions. If multiple supervisor-level
303 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
304 * after any lower-privileged, standard extensions. If multiple
305 * machine-level extensions are listed, they must be ordered
308 * 5. Non-standard extensions (starting with 'X') must be listed after all
309 * standard extensions. If multiple non-standard extensions are listed, they
412 if (ext->id != RISCV_ISA_EXT_INVALID) in riscv_isa_set_ext()
413 set_bit(ext->id, bitmap); in riscv_isa_set_ext()
415 for (int i = 0; i < ext->subset_ext_size; i++) { in riscv_isa_set_ext()
416 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID) in riscv_isa_set_ext()
417 set_bit(ext->subset_ext_ids[i], bitmap); in riscv_isa_set_ext()
433 * well as correct extension dependencies. Some extensions depends on specific
450 if (max_loop_count-- < 0) { in riscv_resolve_isa()
458 if (ext && ext->validate) { in riscv_resolve_isa()
459 ret = ext->validate(ext, resolved_isa); in riscv_resolve_isa()
460 if (ret == -EPROBE_DEFER) { in riscv_resolve_isa()
464 /* Disable the extension entirely */ in riscv_resolve_isa()
486 if ((name_end - name == strlen(ext->name)) && in match_isa_ext()
487 !strncasecmp(name, ext->name, name_end - name)) { in match_isa_ext()
513 pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead."); in riscv_parse_isa_string()
515 * To skip an extension, we find its end. in riscv_parse_isa_string()
516 * As multi-letter extensions must be split from other multi-letter in riscv_parse_isa_string()
517 * extensions with an "_", the end of a multi-letter extension will in riscv_parse_isa_string()
519 * multi-letter extension. in riscv_parse_isa_string()
527 * Workaround for invalid single-letter 's' & 'u' (QEMU). in riscv_parse_isa_string()
530 * multi-letter extension in the ISA string begins with in riscv_parse_isa_string()
533 if (ext[-1] != '_' && ext[1] == 'u') { in riscv_parse_isa_string()
543 * Before attempting to parse the extension itself, we find its end. in riscv_parse_isa_string()
544 * As multi-letter extensions must be split from other multi-letter in riscv_parse_isa_string()
545 * extensions with an "_", the end of a multi-letter extension will in riscv_parse_isa_string()
547 * multi-letter extension. in riscv_parse_isa_string()
551 * the end of the extension, removing any numbers. This may be a in riscv_parse_isa_string()
556 * name portion of an extension, but will be decremented to the last in riscv_parse_isa_string()
558 * A simple re-increment solves this problem. in riscv_parse_isa_string()
568 if (!isdigit(ext_end[-1])) in riscv_parse_isa_string()
571 while (isdigit(*--ext_end)) in riscv_parse_isa_string()
574 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { in riscv_parse_isa_string()
579 while (isdigit(*--ext_end)) in riscv_parse_isa_string()
586 * Things are a little easier for single-letter extensions, as they in riscv_parse_isa_string()
591 * that it arrived at the start of the next extension. in riscv_parse_isa_string()
593 * If we are already on a non-digit, there is nothing to do. Either in riscv_parse_isa_string()
594 * we have a multi-letter extension's _, or the start of an in riscv_parse_isa_string()
595 * extension. in riscv_parse_isa_string()
597 * Otherwise we have found the current extension's major version in riscv_parse_isa_string()
599 * if present. The `p` extension must not appear immediately after in riscv_parse_isa_string()
618 --isa; in riscv_parse_isa_string()
630 * first character of the next extension. As we stop parsing an extension in riscv_parse_isa_string()
631 * on meeting a non-alphanumeric character, an extra increment is needed in riscv_parse_isa_string()
632 * where the succeeding extension is a multi-letter prefixed with an "_". in riscv_parse_isa_string()
676 rc = of_property_read_string(node, "riscv,isa", &isa); in riscv_fill_hwcap_from_isa_string()
679 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); in riscv_fill_hwcap_from_isa_string()
685 pr_warn("Unable to get ISA for the hart - %d\n", cpu); in riscv_fill_hwcap_from_isa_string()
694 * port & dt-bindings were upstreamed, and so can be set in riscv_fill_hwcap_from_isa_string()
695 * unconditionally where `i` is in riscv,isa on DT systems. in riscv_fill_hwcap_from_isa_string()
706 * just the standard V-1.0 but vendors aren't well behaved. in riscv_fill_hwcap_from_isa_string()
707 * Many vendors with T-Head CPU cores which implement the 0.7.1 in riscv_fill_hwcap_from_isa_string()
709 * CPU cores with the ratified spec will contain non-zero in riscv_fill_hwcap_from_isa_string()
717 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); in riscv_fill_hwcap_from_isa_string()
730 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_isa_string()
732 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_isa_string()
747 for (int j = 0; j < ext_list->ext_data_count; j++) { in riscv_fill_cpu_vendor_ext() local
748 const struct riscv_isa_ext_data ext = ext_list->ext_data[j]; in riscv_fill_cpu_vendor_ext()
749 struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu]; in riscv_fill_cpu_vendor_ext()
751 if (of_property_match_string(cpu_node, "riscv,isa-extensions", in riscv_fill_cpu_vendor_ext()
761 set_bit(ext.subset_ext_ids[k], isavendorinfo->isa); in riscv_fill_cpu_vendor_ext()
763 set_bit(ext.id, isavendorinfo->isa); in riscv_fill_cpu_vendor_ext()
780 if (!ext_list->is_initialized) { in riscv_fill_vendor_ext_list()
781 bitmap_copy(ext_list->all_harts_isa_bitmap.isa, in riscv_fill_vendor_ext_list()
782 ext_list->per_hart_isa_bitmap[cpu].isa, in riscv_fill_vendor_ext_list()
784 ext_list->is_initialized = true; in riscv_fill_vendor_ext_list()
786 bitmap_and(ext_list->all_harts_isa_bitmap.isa, in riscv_fill_vendor_ext_list()
787 ext_list->all_harts_isa_bitmap.isa, in riscv_fill_vendor_ext_list()
788 ext_list->per_hart_isa_bitmap[cpu].isa, in riscv_fill_vendor_ext_list()
810 if (!of_property_present(cpu_node, "riscv,isa-extensions")) { in riscv_fill_hwcap_from_ext_list()
818 if (of_property_match_string(cpu_node, "riscv,isa-extensions", in riscv_fill_hwcap_from_ext_list()
819 ext->property) < 0) in riscv_fill_hwcap_from_ext_list()
825 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); in riscv_fill_hwcap_from_ext_list()
840 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_ext_list()
842 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_ext_list()
848 return -ENOENT; in riscv_fill_hwcap_from_ext_list()
869 int i, j; in riscv_fill_hwcap() local
871 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; in riscv_fill_hwcap()
872 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; in riscv_fill_hwcap()
873 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; in riscv_fill_hwcap()
874 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; in riscv_fill_hwcap()
875 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; in riscv_fill_hwcap()
876 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; in riscv_fill_hwcap()
877 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; in riscv_fill_hwcap()
885 pr_info("Falling back to deprecated \"riscv,isa\"\n"); in riscv_fill_hwcap()
917 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) in riscv_fill_hwcap()
919 print_str[j++] = (char)('a' + i); in riscv_fill_hwcap()
920 pr_info("riscv: base ISA extensions %s\n", print_str); in riscv_fill_hwcap()
923 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) in riscv_fill_hwcap()
925 print_str[j++] = (char)('a' + i); in riscv_fill_hwcap()
926 pr_info("riscv: ELF capabilities %s\n", print_str); in riscv_fill_hwcap()
933 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); in riscv_get_elf_hwcap()
944 current->thread.envcfg |= ENVCFG_CBZE; in riscv_user_isa_enable()
953 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
954 * patch site is for an erratum, identified by the 32-bit patch ID. When
956 * further break down patch ID into two 16-bit numbers. The lower 16 bits
960 * patching on a per-site basis will provide non-zero values and implement
995 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); in riscv_cpufeature_patch_func()
996 vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id); in riscv_cpufeature_patch_func()
1000 * RISCV_ISA_EXT_MAX is interpreted as a standard extension. in riscv_cpufeature_patch_func()
1004 * vendor extension. in riscv_cpufeature_patch_func()
1011 if (alt->vendor_id != 0) in riscv_cpufeature_patch_func()
1017 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); in riscv_cpufeature_patch_func()
1022 id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) in riscv_cpufeature_patch_func()
1025 WARN(1, "This extension id:%d is not in ISA extension list", id); in riscv_cpufeature_patch_func()
1033 patch_text_nosync(oldptr, altptr, alt->alt_len); in riscv_cpufeature_patch_func()
1034 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); in riscv_cpufeature_patch_func()