1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
41 /* Per-cpu ISA extensions. */
47  * riscv_isa_extension_base() - Get base extension word
63  * __riscv_isa_extension_available() - Check whether given extension
87 		pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");  in riscv_ext_zicbom_validate()
88 		return -EINVAL;  in riscv_ext_zicbom_validate()
91 		pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");  in riscv_ext_zicbom_validate()
92 		return -EINVAL;  in riscv_ext_zicbom_validate()
101 		pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");  in riscv_ext_zicboz_validate()
102 		return -EINVAL;  in riscv_ext_zicboz_validate()
105 		pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");  in riscv_ext_zicboz_validate()
106 		return -EINVAL;  in riscv_ext_zicboz_validate()
118 	return -EPROBE_DEFER;  in riscv_ext_zca_depends()
127 	return -EPROBE_DEFER;  in riscv_ext_zcd_validate()
134 		return -EINVAL;  in riscv_ext_zcf_validate()
140 	return -EPROBE_DEFER;  in riscv_ext_zcf_validate()
148 		return -EOPNOTSUPP;  in riscv_ext_svadu_validate()
258  * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
269  * - C always implies Zca
270  * - C+F implies Zcf (RV32 only)
271  * - C+D implies Zcd
286  * Ordinarily, for in-kernel data structures, this order is unimportant but
292  * 1. All multi-letter extensions must be separated from other extensions by an
296  *    single-letter extensions and before any higher-privileged extensions.
303  * 3. Standard supervisor-level extensions (starting with 'S') must be listed
304  *    after standard unprivileged extensions.  If multiple supervisor-level
307  * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
308  *    after any lower-privileged, standard extensions.  If multiple
309  *    machine-level extensions are listed, they must be ordered
312  * 5. Non-standard extensions (starting with 'X') must be listed after all
313  *    standard extensions. If multiple non-standard extensions are listed, they
416 	if (ext->id != RISCV_ISA_EXT_INVALID)  in riscv_isa_set_ext()
417 		set_bit(ext->id, bitmap);  in riscv_isa_set_ext()
419 	for (int i = 0; i < ext->subset_ext_size; i++) {  in riscv_isa_set_ext()
420 		if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID)  in riscv_isa_set_ext()
421 			set_bit(ext->subset_ext_ids[i], bitmap);  in riscv_isa_set_ext()
454 		if (max_loop_count-- < 0) {  in riscv_resolve_isa()
462 			if (ext && ext->validate) {  in riscv_resolve_isa()
463 				ret = ext->validate(ext, resolved_isa);  in riscv_resolve_isa()
464 				if (ret == -EPROBE_DEFER) {  in riscv_resolve_isa()
490 		if ((name_end - name == strlen(ext->name)) &&  in match_isa_ext()
491 		    !strncasecmp(name, ext->name, name_end - name)) {  in match_isa_ext()
517 				pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");  in riscv_parse_isa_string()
520 			 * As multi-letter extensions must be split from other multi-letter  in riscv_parse_isa_string()
521 			 * extensions with an "_", the end of a multi-letter extension will  in riscv_parse_isa_string()
523 			 * multi-letter extension.  in riscv_parse_isa_string()
531 			 * Workaround for invalid single-letter 's' & 'u' (QEMU).  in riscv_parse_isa_string()
534 			 * multi-letter extension in the ISA string begins with  in riscv_parse_isa_string()
537 			if (ext[-1] != '_' && ext[1] == 'u') {  in riscv_parse_isa_string()
548 			 * As multi-letter extensions must be split from other multi-letter  in riscv_parse_isa_string()
549 			 * extensions with an "_", the end of a multi-letter extension will  in riscv_parse_isa_string()
551 			 * multi-letter extension.  in riscv_parse_isa_string()
562 			 * A simple re-increment solves this problem.  in riscv_parse_isa_string()
572 			if (!isdigit(ext_end[-1]))  in riscv_parse_isa_string()
575 			while (isdigit(*--ext_end))  in riscv_parse_isa_string()
578 			if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {  in riscv_parse_isa_string()
583 			while (isdigit(*--ext_end))  in riscv_parse_isa_string()
590 			 * Things are a little easier for single-letter extensions, as they  in riscv_parse_isa_string()
597 			 * If we are already on a non-digit, there is nothing to do. Either  in riscv_parse_isa_string()
598 			 * we have a multi-letter extension's _, or the start of an  in riscv_parse_isa_string()
622 				--isa;  in riscv_parse_isa_string()
635 		 * on meeting a non-alphanumeric character, an extra increment is needed  in riscv_parse_isa_string()
636 		 * where the succeeding extension is a multi-letter prefixed with an "_".  in riscv_parse_isa_string()
689 				pr_warn("Unable to get ISA for the hart - %d\n", cpu);  in riscv_fill_hwcap_from_isa_string()
698 		 * port & dt-bindings were upstreamed, and so can be set  in riscv_fill_hwcap_from_isa_string()
710 		 * just the standard V-1.0 but vendors aren't well behaved.  in riscv_fill_hwcap_from_isa_string()
711 		 * Many vendors with T-Head CPU cores which implement the 0.7.1  in riscv_fill_hwcap_from_isa_string()
713 		 * CPU cores with the ratified spec will contain non-zero  in riscv_fill_hwcap_from_isa_string()
721 		riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);  in riscv_fill_hwcap_from_isa_string()
734 			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_isa_string()
736 			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_isa_string()
751 		for (int j = 0; j < ext_list->ext_data_count; j++) {  in riscv_fill_cpu_vendor_ext()
752 			const struct riscv_isa_ext_data ext = ext_list->ext_data[j];  in riscv_fill_cpu_vendor_ext()
753 			struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu];  in riscv_fill_cpu_vendor_ext()
755 			if (of_property_match_string(cpu_node, "riscv,isa-extensions",  in riscv_fill_cpu_vendor_ext()
765 					set_bit(ext.subset_ext_ids[k], isavendorinfo->isa);  in riscv_fill_cpu_vendor_ext()
767 			set_bit(ext.id, isavendorinfo->isa);  in riscv_fill_cpu_vendor_ext()
784 		if (!ext_list->is_initialized) {  in riscv_fill_vendor_ext_list()
785 			bitmap_copy(ext_list->all_harts_isa_bitmap.isa,  in riscv_fill_vendor_ext_list()
786 				    ext_list->per_hart_isa_bitmap[cpu].isa,  in riscv_fill_vendor_ext_list()
788 			ext_list->is_initialized = true;  in riscv_fill_vendor_ext_list()
790 			bitmap_and(ext_list->all_harts_isa_bitmap.isa,  in riscv_fill_vendor_ext_list()
791 				   ext_list->all_harts_isa_bitmap.isa,  in riscv_fill_vendor_ext_list()
792 				   ext_list->per_hart_isa_bitmap[cpu].isa,  in riscv_fill_vendor_ext_list()
814 			return -ENOENT;  in has_thead_homogeneous_vlenb()
821 				return -ENOENT;  in has_thead_homogeneous_vlenb()
827 			return -ENOENT;  in has_thead_homogeneous_vlenb()
855 		if (!of_property_present(cpu_node, "riscv,isa-extensions")) {  in riscv_fill_hwcap_from_ext_list()
863 			if (of_property_match_string(cpu_node, "riscv,isa-extensions",  in riscv_fill_hwcap_from_ext_list()
864 						     ext->property) < 0)  in riscv_fill_hwcap_from_ext_list()
870 		riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);  in riscv_fill_hwcap_from_ext_list()
885 			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_ext_list()
887 			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);  in riscv_fill_hwcap_from_ext_list()
904 		return -ENOENT;  in riscv_fill_hwcap_from_ext_list()
927 	isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;  in riscv_fill_hwcap()
928 	isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;  in riscv_fill_hwcap()
929 	isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;  in riscv_fill_hwcap()
930 	isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;  in riscv_fill_hwcap()
931 	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;  in riscv_fill_hwcap()
932 	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;  in riscv_fill_hwcap()
933 	isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;  in riscv_fill_hwcap()
990 	hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));  in riscv_get_elf_hwcap()
1001 		current->thread.envcfg |= ENVCFG_CBZE;  in riscv_user_isa_enable()
1010  * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
1011  * patch site is for an erratum, identified by the 32-bit patch ID. When
1013  * further break down patch ID into two 16-bit numbers. The lower 16 bits
1017  * patching on a per-site basis will provide non-zero values and implement
1030 		 * supported block size order, or zero when it doesn't  in riscv_cpufeature_patch_check()
1031 		 * matter. If the current block size exceeds the maximum,  in riscv_cpufeature_patch_check()
1052 		id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);  in riscv_cpufeature_patch_func()
1053 		vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id);  in riscv_cpufeature_patch_func()
1068 			if (alt->vendor_id != 0)  in riscv_cpufeature_patch_func()
1074 			value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);  in riscv_cpufeature_patch_func()
1079 								    id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE))  in riscv_cpufeature_patch_func()
1090 		patch_text_nosync(oldptr, altptr, alt->alt_len);  in riscv_cpufeature_patch_func()
1091 		riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);  in riscv_cpufeature_patch_func()