Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:f_
1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #define RV_INSN_OPCODE_MASK GENMASK(6, 0)
14 #define RV_INSN_OPCODE_OPOFF 0
17 #define RV_ENCODE_FUNCT3(f_) (RVG_FUNCT3_##f_ << RV_INSN_FUNCT3_OPOFF) argument
18 #define RV_ENCODE_FUNCT12(f_) (RVG_FUNCT12_##f_ << RV_INSN_FUNCT12_OPOFF) argument
20 /* The bit field of immediate value in I-type instruction */
24 #define RV_I_IMM_11_0_OFF 0
25 #define RV_I_IMM_11_0_MASK GENMASK(11, 0)
27 /* The bit field of immediate value in J-type instruction */
36 #define RV_J_IMM_10_1_MASK GENMASK(9, 0)
37 #define RV_J_IMM_11_MASK GENMASK(0, 0)
38 #define RV_J_IMM_19_12_MASK GENMASK(7, 0)
41 * U-type IMMs contain the upper 20bits [31:20] of an immediate with
46 #define RV_U_IMM_31_12_OPOFF 0
49 /* The bit field of immediate value in B-type instruction */
58 #define RV_B_IMM_10_5_MASK GENMASK(5, 0)
59 #define RV_B_IMM_4_1_MASK GENMASK(3, 0)
60 #define RV_B_IMM_11_MASK GENMASK(0, 0)
66 #define RVG_RS1_MASK GENMASK(4, 0)
67 #define RVG_RS2_MASK GENMASK(4, 0)
68 #define RVG_RD_MASK GENMASK(4, 0)
73 #define RVC_J_IMM_9_8_OPOFF 9
87 #define RVC_J_IMM_4_MASK GENMASK(0, 0)
88 #define RVC_J_IMM_9_8_MASK GENMASK(1, 0)
89 #define RVC_J_IMM_10_MASK GENMASK(0, 0)
90 #define RVC_J_IMM_6_MASK GENMASK(0, 0)
91 #define RVC_J_IMM_7_MASK GENMASK(0, 0)
92 #define RVC_J_IMM_3_1_MASK GENMASK(2, 0)
93 #define RVC_J_IMM_5_MASK GENMASK(0, 0)
106 #define RVC_B_IMM_4_3_MASK GENMASK(1, 0)
107 #define RVC_B_IMM_7_6_MASK GENMASK(1, 0)
108 #define RVC_B_IMM_2_1_MASK GENMASK(1, 0)
109 #define RVC_B_IMM_5_MASK GENMASK(0, 0)
117 #define RVC_INSN_OPCODE_MASK GENMASK(1, 0)
118 #define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF) argument
119 #define RVC_ENCODE_FUNCT4(f_) (RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF) argument
135 #define RVC_C2_RS1_MASK GENMASK(4, 0)
138 #define RVG_OPCODE_FENCE 0x0f
139 #define RVG_OPCODE_AUIPC 0x17
140 #define RVG_OPCODE_BRANCH 0x63
141 #define RVG_OPCODE_JALR 0x67
142 #define RVG_OPCODE_JAL 0x6f
143 #define RVG_OPCODE_SYSTEM 0x73
145 #define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)
149 #define RVFDQ_FL_FS_WIDTH_MASK GENMASK(2, 0)
153 #define RVFDQ_OPCODE_FL 0x07
154 #define RVFDQ_OPCODE_FS 0x27
157 #define RVV_OPCODE_VECTOR 0x57
158 #define RVV_VL_VS_WIDTH_8 0
166 #define RVC_OPCODE_C0 0x0
167 #define RVC_OPCODE_C1 0x1
168 #define RVC_OPCODE_C2 0x2
170 /* parts of funct3 code for I, M, A extension*/
171 #define RVG_FUNCT3_JALR 0x0
172 #define RVG_FUNCT3_BEQ 0x0
173 #define RVG_FUNCT3_BNE 0x1
174 #define RVG_FUNCT3_BLT 0x4
175 #define RVG_FUNCT3_BGE 0x5
176 #define RVG_FUNCT3_BLTU 0x6
177 #define RVG_FUNCT3_BGEU 0x7
180 #define RVC_FUNCT3_C_BEQZ 0x6
181 #define RVC_FUNCT3_C_BNEZ 0x7
182 #define RVC_FUNCT3_C_J 0x5
183 #define RVC_FUNCT3_C_JAL 0x1
184 #define RVC_FUNCT4_C_JR 0x8
185 #define RVC_FUNCT4_C_JALR 0x9
186 #define RVC_FUNCT4_C_EBREAK 0x9
188 #define RVG_FUNCT12_EBREAK 0x1
189 #define RVG_FUNCT12_SRET 0x102
227 #define RVC_MASK_C_EBREAK 0xffff
228 #define RVG_MASK_EBREAK 0xffffffff
229 #define RVG_MASK_SRET 0xffffffff
231 #define __INSN_LENGTH_MASK _UL(0x3)
232 #define __INSN_LENGTH_GE_32 _UL(0x3)
233 #define __INSN_OPCODE_MASK _UL(0x7F)
244 /* C.JAL is an RV32C-only instruction */
247 #define riscv_insn_is_c_jal(opcode) 0
281 (code & RVC_INSN_J_RS1_MASK) != 0; in riscv_insn_is_c_jr()
287 (code & RVC_INSN_J_RS1_MASK) != 0; in riscv_insn_is_c_jalr()
290 #define INSN_MATCH_LB 0x3
291 #define INSN_MASK_LB 0x707f
292 #define INSN_MATCH_LH 0x1003
293 #define INSN_MASK_LH 0x707f
294 #define INSN_MATCH_LW 0x2003
295 #define INSN_MASK_LW 0x707f
296 #define INSN_MATCH_LD 0x3003
297 #define INSN_MASK_LD 0x707f
298 #define INSN_MATCH_LBU 0x4003
299 #define INSN_MASK_LBU 0x707f
300 #define INSN_MATCH_LHU 0x5003
301 #define INSN_MASK_LHU 0x707f
302 #define INSN_MATCH_LWU 0x6003
303 #define INSN_MASK_LWU 0x707f
304 #define INSN_MATCH_SB 0x23
305 #define INSN_MASK_SB 0x707f
306 #define INSN_MATCH_SH 0x1023
307 #define INSN_MASK_SH 0x707f
308 #define INSN_MATCH_SW 0x2023
309 #define INSN_MASK_SW 0x707f
310 #define INSN_MATCH_SD 0x3023
311 #define INSN_MASK_SD 0x707f
313 #define INSN_MATCH_C_LD 0x6000
314 #define INSN_MASK_C_LD 0xe003
315 #define INSN_MATCH_C_SD 0xe000
316 #define INSN_MASK_C_SD 0xe003
317 #define INSN_MATCH_C_LW 0x4000
318 #define INSN_MASK_C_LW 0xe003
319 #define INSN_MATCH_C_SW 0xc000
320 #define INSN_MASK_C_SW 0xe003
321 #define INSN_MATCH_C_LDSP 0x6002
322 #define INSN_MASK_C_LDSP 0xe003
323 #define INSN_MATCH_C_SDSP 0xe002
324 #define INSN_MASK_C_SDSP 0xe003
325 #define INSN_MATCH_C_LWSP 0x4002
326 #define INSN_MASK_C_LWSP 0xe003
327 #define INSN_MATCH_C_SWSP 0xc002
328 #define INSN_MASK_C_SWSP 0xe003
330 #define INSN_OPCODE_MASK 0x007c
334 #define INSN_MASK_WFI 0xffffffff
335 #define INSN_MATCH_WFI 0x10500073
337 #define INSN_MASK_WRS 0xffffffff
338 #define INSN_MATCH_WRS 0x00d00073
340 #define INSN_MATCH_CSRRW 0x1073
341 #define INSN_MASK_CSRRW 0x707f
342 #define INSN_MATCH_CSRRS 0x2073
343 #define INSN_MASK_CSRRS 0x707f
344 #define INSN_MATCH_CSRRC 0x3073
345 #define INSN_MASK_CSRRC 0x707f
346 #define INSN_MATCH_CSRRWI 0x5073
347 #define INSN_MASK_CSRRWI 0x707f
348 #define INSN_MATCH_CSRRSI 0x6073
349 #define INSN_MASK_CSRRSI 0x707f
350 #define INSN_MATCH_CSRRCI 0x7073
351 #define INSN_MASK_CSRRCI 0x707f
353 #define INSN_MATCH_FLW 0x2007
354 #define INSN_MASK_FLW 0x707f
355 #define INSN_MATCH_FLD 0x3007
356 #define INSN_MASK_FLD 0x707f
357 #define INSN_MATCH_FLQ 0x4007
358 #define INSN_MASK_FLQ 0x707f
359 #define INSN_MATCH_FSW 0x2027
360 #define INSN_MASK_FSW 0x707f
361 #define INSN_MATCH_FSD 0x3027
362 #define INSN_MASK_FSD 0x707f
363 #define INSN_MATCH_FSQ 0x4027
364 #define INSN_MASK_FSQ 0x707f
366 #define INSN_MATCH_C_FLD 0x2000
367 #define INSN_MASK_C_FLD 0xe003
368 #define INSN_MATCH_C_FLW 0x6000
369 #define INSN_MASK_C_FLW 0xe003
370 #define INSN_MATCH_C_FSD 0xa000
371 #define INSN_MASK_C_FSD 0xe003
372 #define INSN_MATCH_C_FSW 0xe000
373 #define INSN_MASK_C_FSW 0xe003
374 #define INSN_MATCH_C_FLDSP 0x2002
375 #define INSN_MASK_C_FLDSP 0xe003
376 #define INSN_MATCH_C_FSDSP 0xa002
377 #define INSN_MASK_C_FSDSP 0xe003
378 #define INSN_MATCH_C_FLWSP 0x6002
379 #define INSN_MASK_C_FLWSP 0xe003
380 #define INSN_MATCH_C_FSWSP 0xe002
381 #define INSN_MASK_C_FSWSP 0xe003
383 #define INSN_MATCH_C_LHU 0x8400
384 #define INSN_MASK_C_LHU 0xfc43
385 #define INSN_MATCH_C_LH 0x8440
386 #define INSN_MASK_C_LH 0xfc43
387 #define INSN_MATCH_C_SH 0x8c00
388 #define INSN_MASK_C_SH 0xfc43
390 #define INSN_16BIT_MASK 0x3
395 ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
398 ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
401 (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
408 #define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
409 #define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
411 #define GET_SP(regs) (*REG_PTR(2, 0, regs))
415 (s32)(((insn) >> 7) & 0x1f))
421 #define MASK_RX 0x1f
429 #define MASK_FUNCT3 0x7000
433 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
434 #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
436 #define RV_X(X, s, n) RV_X_MASK(X, s, ((1 << (n)) - 1))
448 #define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
530 * Get the immediate from a J-type instruction.
541 * Update a J-type instruction with an immediate value.
557 * Put together one immediate from a U-type and I-type instruction pair.
559 * The U-type contains an upper immediate, meaning bits[31:12] with [11:0]
560 * being zero, while the I-type contains a 12bit immediate.
579 * Update a set of two instructions (U-type + I-type) with an immediate value.
581 * Used for example in auipc+jalrs pairs the U-type instructions contains
582 * a 20bit upper immediate representing bits[31:12], while the I-type
583 * instruction contains a 12bit immediate representing bits[11:0].
586 * considered as signed values, so if the I-type immediate becomes
587 * negative (BIT(11) set) the U-type part gets adjusted.